446 lines
15 KiB
Systemverilog
Executable File
446 lines
15 KiB
Systemverilog
Executable File
// Generated by CIRCT firtool-1.62.0
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// Standard header to adapt well known macros for prints and assertions.
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// Users can define 'PRINTF_COND' to add an extra gate to prints.
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`ifndef PRINTF_COND_
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`ifdef PRINTF_COND
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`define PRINTF_COND_ (`PRINTF_COND)
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`else // PRINTF_COND
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`define PRINTF_COND_ 1
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`endif // PRINTF_COND
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`endif // not def PRINTF_COND_
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// VCS coverage exclude_file
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module regfile_32x32(
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input [4:0] R0_addr,
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input R0_en,
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R0_clk,
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output [31:0] R0_data,
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input [4:0] R1_addr,
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input R1_en,
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R1_clk,
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output [31:0] R1_data,
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input [4:0] W0_addr,
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input W0_en,
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W0_clk,
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input [31:0] W0_data
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);
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reg [31:0] Memory[0:31];
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always @(posedge W0_clk) begin
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if (W0_en & 1'h1)
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Memory[W0_addr] <= W0_data;
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end // always @(posedge)
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assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
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assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
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endmodule
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module Core(
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input clock,
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reset,
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output [31:0] io_imem_addr,
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input [31:0] io_imem_inst,
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output [31:0] io_dmem_addr,
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input [31:0] io_dmem_rdata,
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output io_dmem_wen,
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output [31:0] io_dmem_wdata,
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output io_exit
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);
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wire [31:0] _regfile_ext_R0_data;
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wire [31:0] _regfile_ext_R1_data;
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reg [31:0] pc_reg;
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wire [31:0] _pc_plus4_T = pc_reg + 32'h4;
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wire [9:0] _GEN = {io_imem_inst[31:28], io_imem_inst[5:0]};
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wire jmp_flg = io_imem_inst[31:28] == 4'h3 | _GEN == 10'h8;
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wire [31:0] rs_data = (|(io_imem_inst[25:21])) ? _regfile_ext_R1_data : 32'h0;
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wire [31:0] rt_data = (|(io_imem_inst[20:16])) ? _regfile_ext_R0_data : 32'h0;
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wire [11:0] _GEN_0 = {io_imem_inst[31:26], io_imem_inst[5:0]};
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wire _csignals_T_5 = _GEN_0 == 12'h20;
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wire _csignals_T_7 = io_imem_inst[31:28] == 4'h8;
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wire _csignals_T_9 = _GEN_0 == 12'h22;
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wire _csignals_T_11 = _GEN_0 == 12'h24;
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wire _csignals_T_13 = _GEN_0 == 12'h25;
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wire _csignals_T_15 = _GEN_0 == 12'h26;
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wire _csignals_T_17 = io_imem_inst[31:28] == 4'hC;
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wire _csignals_T_19 = io_imem_inst[31:28] == 4'hD;
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wire _csignals_T_21 = _GEN_0 == 12'h2A;
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wire _csignals_T_23 = io_imem_inst[31:28] == 4'h4;
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wire _csignals_T_25 = io_imem_inst[31:28] == 4'h5;
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wire [16:0] _GEN_1 = {io_imem_inst[31:21], io_imem_inst[5:0]};
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wire _csignals_T_27 = _GEN_1 == 17'h0;
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wire _csignals_T_29 = _GEN_1 == 17'h2;
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wire _csignals_T_31 = _GEN_1 == 17'h3;
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wire _csignals_T_33 = io_imem_inst[31:28] == 4'h3;
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wire _csignals_T_35 = _GEN == 10'h8;
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wire [4:0] csignals_0 =
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_csignals_T_5 | _csignals_T_7
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? 5'h1
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: _csignals_T_9
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? 5'h2
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: _csignals_T_11
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? 5'h3
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: _csignals_T_13
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? 5'h4
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: _csignals_T_15
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? 5'h5
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: _csignals_T_17
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? 5'h3
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: _csignals_T_19
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? 5'h4
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: _csignals_T_21
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? 5'h9
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: _csignals_T_23
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? 5'hB
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: _csignals_T_25
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? 5'hC
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: _csignals_T_27
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? 5'h6
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: _csignals_T_29
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? 5'h7
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: _csignals_T_31
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? 5'h8
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: _csignals_T_33
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? 5'h1
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: _csignals_T_35 ? 5'hD : 5'h0;
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wire _GEN_2 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
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wire _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_2;
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wire [1:0] csignals_1 =
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_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 | ~_csignals_T_33
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? 2'h1
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: 2'h2;
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wire [2:0] _csignals_T_85 =
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_csignals_T_5
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? 3'h1
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: _csignals_T_7
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? 3'h2
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: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
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? 3'h1
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: _csignals_T_17 | _csignals_T_19
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? 3'h2
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: _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
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wire _GEN_4 = _csignals_T_23 | _csignals_T_25;
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wire _GEN_5 =
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_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
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wire [1:0] _csignals_T_136 =
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_GEN_5 ? 2'h1 : _GEN_4 ? 2'h0 : _GEN_2 ? 2'h1 : {2{_csignals_T_33}};
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wire _op1_data_T = csignals_1 == 2'h1;
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wire _op1_data_T_1 = csignals_1 == 2'h2;
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wire [31:0] op1_data = _op1_data_T ? rs_data : _op1_data_T_1 ? pc_reg : 32'h0;
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wire [31:0] op2_data =
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_csignals_T_85 == 3'h1
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? rt_data
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: _csignals_T_85 == 3'h2
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? {{16{io_imem_inst[15]}}, io_imem_inst[15:0]}
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: _csignals_T_85 == 3'h4 ? {4'h0, io_imem_inst[25:0], 2'h0} : 32'h0;
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wire _alu_out_T = csignals_0 == 5'h1;
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wire [31:0] _alu_out_T_1 = op1_data + op2_data;
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wire _alu_out_T_3 = csignals_0 == 5'h2;
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wire [31:0] _alu_out_T_4 = op1_data - op2_data;
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wire _alu_out_T_6 = csignals_0 == 5'h3;
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wire [31:0] _alu_out_T_7 = op1_data & op2_data;
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wire _alu_out_T_8 = csignals_0 == 5'h4;
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wire [31:0] _alu_out_T_9 = op1_data | op2_data;
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wire _alu_out_T_10 = csignals_0 == 5'h5;
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wire [31:0] _alu_out_T_11 = op1_data ^ op2_data;
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wire _alu_out_T_12 = csignals_0 == 5'h6;
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wire [62:0] _alu_out_T_14 = {31'h0, op1_data} << op2_data[4:0];
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wire _alu_out_T_16 = csignals_0 == 5'h7;
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wire [31:0] _GEN_6 = {27'h0, op2_data[4:0]};
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wire [31:0] _alu_out_T_18 = op1_data >> _GEN_6;
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wire _alu_out_T_19 = csignals_0 == 5'h8;
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wire [31:0] _alu_out_T_22 = $signed($signed(op1_data) >>> _GEN_6);
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wire _alu_out_T_24 = csignals_0 == 5'h9;
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wire _alu_out_T_28 = csignals_0 == 5'hD;
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wire [31:0] _GEN_7 = {31'h0, $signed(op1_data) < $signed(op2_data)};
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wire [31:0] alu_out =
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_alu_out_T
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? _alu_out_T_1
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: _alu_out_T_3
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? _alu_out_T_4
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: _alu_out_T_6
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? _alu_out_T_7
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: _alu_out_T_8
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? _alu_out_T_9
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: _alu_out_T_10
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? _alu_out_T_11
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: _alu_out_T_12
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? _alu_out_T_14[31:0]
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: _alu_out_T_16
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? _alu_out_T_18
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: _alu_out_T_19
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? _alu_out_T_22
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: _alu_out_T_24
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? _GEN_7
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: _alu_out_T_28 ? op1_data : 32'h0;
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wire _br_flg_T_3 = op1_data == op2_data;
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wire br_flg =
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csignals_0 == 5'hB ? _br_flg_T_3 : csignals_0 == 5'hC & ~_br_flg_T_3;
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wire [31:0] br_target = {{14{io_imem_inst[15]}}, io_imem_inst[15:0], 2'h0} + pc_reg;
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wire [31:0] wb_data =
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_csignals_T_136 == 2'h2 ? io_dmem_rdata : (&_csignals_T_136) ? _pc_plus4_T : alu_out;
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`ifndef SYNTHESIS
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always @(posedge clock) begin
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if ((`PRINTF_COND_) & ~reset) begin
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$fwrite(32'h80000002, "---------------\n");
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$fwrite(32'h80000002, "io.pc: 0x%x\ninst: 0x%x \n", pc_reg, io_imem_inst);
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$fwrite(32'h80000002, "pc_next: 0x%x\n",
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br_flg ? br_target : jmp_flg ? alu_out : _pc_plus4_T);
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$fwrite(32'h80000002, "rs_addr: 0x%x\n", io_imem_inst[25:21]);
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$fwrite(32'h80000002, "rd_addr: 0x%x\n", io_imem_inst[15:11]);
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$fwrite(32'h80000002, "rs_data: 0x%x\n", rs_data);
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$fwrite(32'h80000002, "wb_data: 0x%x\n", wb_data);
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$fwrite(32'h80000002, "---------------\n");
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end
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end // always @(posedge)
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`endif // not def SYNTHESIS
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always @(posedge clock) begin
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if (reset)
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pc_reg <= 32'h0;
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else if (br_flg)
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pc_reg <= br_target;
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else if (jmp_flg) begin
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if (_alu_out_T)
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pc_reg <= _alu_out_T_1;
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else if (_alu_out_T_3)
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pc_reg <= _alu_out_T_4;
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else if (_alu_out_T_6)
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pc_reg <= _alu_out_T_7;
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else if (_alu_out_T_8)
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pc_reg <= _alu_out_T_9;
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else if (_alu_out_T_10)
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pc_reg <= _alu_out_T_11;
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else if (_alu_out_T_12)
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pc_reg <= _alu_out_T_14[31:0];
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else if (_alu_out_T_16)
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pc_reg <= _alu_out_T_18;
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else if (_alu_out_T_19)
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pc_reg <= _alu_out_T_22;
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else if (_alu_out_T_24)
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pc_reg <= _GEN_7;
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else if (_alu_out_T_28) begin
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if (_op1_data_T)
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pc_reg <= rs_data;
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else if (~_op1_data_T_1)
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pc_reg <= 32'h0;
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end
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else
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pc_reg <= 32'h0;
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end
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else
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pc_reg <= _pc_plus4_T;
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end // always @(posedge)
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regfile_32x32 regfile_ext (
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.R0_addr (io_imem_inst[20:16]),
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.R0_en (1'h1),
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.R0_clk (clock),
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.R0_data (_regfile_ext_R0_data),
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.R1_addr (io_imem_inst[25:21]),
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.R1_en (1'h1),
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.R1_clk (clock),
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.R1_data (_regfile_ext_R1_data),
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.W0_addr (io_imem_inst[15:11]),
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.W0_en
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(_GEN_5 | ~_GEN_4
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& (_csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33)),
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.W0_clk (clock),
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.W0_data (wb_data)
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);
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assign io_imem_addr = pc_reg;
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assign io_dmem_addr = alu_out;
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assign io_dmem_wen = 1'h0;
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assign io_dmem_wdata = rt_data;
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assign io_exit = io_imem_inst == 32'h114514;
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endmodule
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// VCS coverage exclude_file
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module mem_4096x8(
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input [11:0] R0_addr,
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input R0_en,
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R0_clk,
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output [7:0] R0_data,
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input [11:0] R1_addr,
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input R1_en,
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R1_clk,
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output [7:0] R1_data,
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input [11:0] R2_addr,
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input R2_en,
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R2_clk,
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output [7:0] R2_data,
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input [11:0] R3_addr,
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input R3_en,
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R3_clk,
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output [7:0] R3_data,
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input [11:0] R4_addr,
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input R4_en,
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R4_clk,
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output [7:0] R4_data,
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input [11:0] R5_addr,
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input R5_en,
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R5_clk,
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output [7:0] R5_data,
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input [11:0] R6_addr,
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input R6_en,
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R6_clk,
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output [7:0] R6_data,
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input [11:0] R7_addr,
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input R7_en,
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R7_clk,
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output [7:0] R7_data,
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input [11:0] W0_addr,
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input W0_en,
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W0_clk,
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input [7:0] W0_data,
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input [11:0] W1_addr,
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input W1_en,
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W1_clk,
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input [7:0] W1_data,
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input [11:0] W2_addr,
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input W2_en,
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W2_clk,
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input [7:0] W2_data,
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input [11:0] W3_addr,
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input W3_en,
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W3_clk,
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input [7:0] W3_data
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);
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reg [7:0] Memory[0:4095];
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always @(posedge W0_clk) begin
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if (W0_en & 1'h1)
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Memory[W0_addr] <= W0_data;
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if (W1_en & 1'h1)
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Memory[W1_addr] <= W1_data;
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if (W2_en & 1'h1)
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Memory[W2_addr] <= W2_data;
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if (W3_en & 1'h1)
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Memory[W3_addr] <= W3_data;
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end // always @(posedge)
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`ifdef ENABLE_INITIAL_MEM_
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initial
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$readmemh("src/hex/addi.hex", Memory);
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`endif // ENABLE_INITIAL_MEM_
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assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
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assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
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assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
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assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
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assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
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assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
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assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
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assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
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endmodule
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module Memory(
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input clock,
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input [31:0] io_imem_addr,
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output [31:0] io_imem_inst,
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input [31:0] io_dmem_addr,
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output [31:0] io_dmem_rdata,
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input io_dmem_wen,
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input [31:0] io_dmem_wdata
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);
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wire [7:0] _mem_ext_R0_data;
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wire [7:0] _mem_ext_R1_data;
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wire [7:0] _mem_ext_R2_data;
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wire [7:0] _mem_ext_R3_data;
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wire [7:0] _mem_ext_R4_data;
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wire [7:0] _mem_ext_R5_data;
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wire [7:0] _mem_ext_R6_data;
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wire [7:0] _mem_ext_R7_data;
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wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3;
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wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2;
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wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1;
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mem_4096x8 mem_ext (
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.R0_addr (io_imem_addr[11:0]),
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.R0_en (1'h1),
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.R0_clk (clock),
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.R0_data (_mem_ext_R0_data),
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.R1_addr (io_imem_addr[11:0] + 12'h1),
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.R1_en (1'h1),
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.R1_clk (clock),
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.R1_data (_mem_ext_R1_data),
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.R2_addr (io_imem_addr[11:0] + 12'h2),
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.R2_en (1'h1),
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.R2_clk (clock),
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.R2_data (_mem_ext_R2_data),
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.R3_addr (io_imem_addr[11:0] + 12'h3),
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.R3_en (1'h1),
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.R3_clk (clock),
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.R3_data (_mem_ext_R3_data),
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.R4_addr (io_dmem_addr[11:0]),
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.R4_en (1'h1),
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.R4_clk (clock),
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.R4_data (_mem_ext_R4_data),
|
|
.R5_addr (_io_dmem_rdata_T_6),
|
|
.R5_en (1'h1),
|
|
.R5_clk (clock),
|
|
.R5_data (_mem_ext_R5_data),
|
|
.R6_addr (_io_dmem_rdata_T_3),
|
|
.R6_en (1'h1),
|
|
.R6_clk (clock),
|
|
.R6_data (_mem_ext_R6_data),
|
|
.R7_addr (_io_dmem_rdata_T),
|
|
.R7_en (1'h1),
|
|
.R7_clk (clock),
|
|
.R7_data (_mem_ext_R7_data),
|
|
.W0_addr (_io_dmem_rdata_T),
|
|
.W0_en (io_dmem_wen),
|
|
.W0_clk (clock),
|
|
.W0_data (io_dmem_wdata[31:24]),
|
|
.W1_addr (_io_dmem_rdata_T_3),
|
|
.W1_en (io_dmem_wen),
|
|
.W1_clk (clock),
|
|
.W1_data (io_dmem_wdata[23:16]),
|
|
.W2_addr (_io_dmem_rdata_T_6),
|
|
.W2_en (io_dmem_wen),
|
|
.W2_clk (clock),
|
|
.W2_data (io_dmem_wdata[15:8]),
|
|
.W3_addr (io_dmem_addr[11:0]),
|
|
.W3_en (io_dmem_wen),
|
|
.W3_clk (clock),
|
|
.W3_data (io_dmem_wdata[7:0])
|
|
);
|
|
assign io_imem_inst =
|
|
{_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
|
|
assign io_dmem_rdata =
|
|
{_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
|
|
endmodule
|
|
|
|
module TopOrigin(
|
|
input clock,
|
|
reset,
|
|
output io_exit
|
|
);
|
|
|
|
wire [31:0] _memory_io_imem_inst;
|
|
wire [31:0] _memory_io_dmem_rdata;
|
|
wire [31:0] _core_io_imem_addr;
|
|
wire [31:0] _core_io_dmem_addr;
|
|
wire _core_io_dmem_wen;
|
|
wire [31:0] _core_io_dmem_wdata;
|
|
Core core (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_imem_addr (_core_io_imem_addr),
|
|
.io_imem_inst (_memory_io_imem_inst),
|
|
.io_dmem_addr (_core_io_dmem_addr),
|
|
.io_dmem_rdata (_memory_io_dmem_rdata),
|
|
.io_dmem_wen (_core_io_dmem_wen),
|
|
.io_dmem_wdata (_core_io_dmem_wdata),
|
|
.io_exit (io_exit)
|
|
);
|
|
Memory memory (
|
|
.clock (clock),
|
|
.io_imem_addr (_core_io_imem_addr),
|
|
.io_imem_inst (_memory_io_imem_inst),
|
|
.io_dmem_addr (_core_io_dmem_addr),
|
|
.io_dmem_rdata (_memory_io_dmem_rdata),
|
|
.io_dmem_wen (_core_io_dmem_wen),
|
|
.io_dmem_wdata (_core_io_dmem_wdata)
|
|
);
|
|
endmodule
|
|
|