55 lines
1.4 KiB
Systemverilog
Executable File
55 lines
1.4 KiB
Systemverilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/12/28 11:28:52
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// Design Name:
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// Module Name: Regfile
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module regfile_32x32(
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input [4:0] R0_addr,
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input R0_en,
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R0_clk,
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output [31:0] R0_data,
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input [4:0] R1_addr,
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input R1_en,
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R1_clk,
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output [31:0] R1_data,
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input [4:0] W0_addr,
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input W0_en,
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W0_clk,
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output [3:0] io_anodes,
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output [6:0] io_segments,
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input [31:0] W0_data
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);
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reg [31:0] Memory[0:31];
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always @(posedge W0_clk) begin
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if (W0_en & 1'h1)
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Memory[W0_addr] <= W0_data;
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end // always @(posedge)
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assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
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assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
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wire [31:0] reg16_value = Memory[16];
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DynamicDisplay display (
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.clock (W0_clk),
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.reset (1'b0),
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.reg_result (reg16_value),
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.io_anodes (io_anodes),
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.io_segments (io_segments)
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);
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endmodule
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