59 lines
1.4 KiB
Systemverilog
Executable File
59 lines
1.4 KiB
Systemverilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/12/28 11:28:52
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// Design Name:
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// Module Name: Regfile
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module regfile_32x32(
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input [4:0] R0_addr,
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input R0_en,
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R0_clk,
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output [31:0] R0_data,
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input [4:0] R1_addr,
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input R1_en,
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R1_clk,
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output [31:0] R1_data,
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input [4:0] W0_addr,
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input W0_en,
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W0_clk,
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input [31:0] W0_data
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);
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reg [31:0] Memory[0:31];
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reg _R0_en_d0;
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reg [4:0] _R0_addr_d0;
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always @(posedge R0_clk) begin
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_R0_en_d0 <= R0_en;
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_R0_addr_d0 <= R0_addr;
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end // always @(posedge)
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reg _R1_en_d0;
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reg [4:0] _R1_addr_d0;
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always @(posedge R1_clk) begin
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_R1_en_d0 <= R1_en;
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_R1_addr_d0 <= R1_addr;
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end // always @(posedge)
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always @(posedge W0_clk) begin
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if (W0_en & 1'h1)
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Memory[W0_addr] <= W0_data;
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end // always @(posedge)
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assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
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assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
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endmodule
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