89 lines
3.5 KiB
C++
89 lines
3.5 KiB
C++
#ifndef RISCV32_BACKEND_H
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#define RISCV32_BACKEND_H
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#include "IR.h"
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#include <string>
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#include <vector>
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#include <map>
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#include <set>
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#include <memory>
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#include <iostream>
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#include <functional> // For std::function
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namespace sysy {
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class RISCv32CodeGen {
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public:
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enum class PhysicalReg {
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ZERO, RA, SP, GP, TP, T0, T1, T2, S0, S1, A0, A1, A2, A3, A4, A5, A6, A7, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, T3, T4, T5, T6
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};
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// Move DAGNode and RegAllocResult to public section
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struct DAGNode {
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enum NodeKind { CONSTANT, LOAD, STORE, BINARY, CALL, RETURN, BRANCH, ALLOCA_ADDR }; // Added ALLOCA_ADDR
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NodeKind kind;
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Value* value = nullptr; // For IR Value
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std::string inst; // Generated RISC-V instruction(s) for this node
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std::string result_vreg; // Virtual register assigned to this node's result
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std::vector<DAGNode*> operands;
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std::vector<DAGNode*> users; // For debugging and potentially optimizations
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DAGNode(NodeKind k) : kind(k) {}
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// Debugging / helper
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std::string getNodeKindString() const {
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switch (kind) {
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case CONSTANT: return "CONSTANT";
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case LOAD: return "LOAD";
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case STORE: return "STORE";
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case BINARY: return "BINARY";
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case CALL: return "CALL";
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case RETURN: return "RETURN";
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case BRANCH: return "BRANCH";
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case ALLOCA_ADDR: return "ALLOCA_ADDR";
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default: return "UNKNOWN";
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}
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}
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};
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struct RegAllocResult {
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std::map<std::string, PhysicalReg> vreg_to_preg; // Virtual register to Physical Register mapping
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std::map<Value*, int> stack_map; // Value (AllocaInst) to stack offset
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int stack_size = 0; // Total stack frame size for locals and spills
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};
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RISCv32CodeGen(Module* mod) : module(mod) {}
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std::string code_gen();
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std::string module_gen();
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std::string function_gen(Function* func);
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std::string basicBlock_gen(BasicBlock* bb, const RegAllocResult& alloc);
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// DAG related
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std::vector<std::unique_ptr<DAGNode>> build_dag(BasicBlock* bb);
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void select_instructions(DAGNode* node, const RegAllocResult& alloc);
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void emit_instructions(DAGNode* node, std::vector<std::string>& insts, const RegAllocResult& alloc, std::set<DAGNode*>& emitted_nodes); // Add emitted_nodes set
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// Register Allocation related
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std::map<Instruction*, std::set<std::string>> liveness_analysis(Function* func);
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std::map<std::string, std::set<std::string>> build_interference_graph(
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const std::map<Instruction*, std::set<std::string>>& live_sets);
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void color_graph(std::map<std::string, PhysicalReg>& vreg_to_preg,
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const std::map<std::string, std::set<std::string>>& interference_graph);
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RegAllocResult register_allocation(Function* func);
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void eliminate_phi(Function* func); // Phi elimination is typically done before DAG building
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// Utility
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std::string reg_to_string(PhysicalReg reg);
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void print_dag(const std::vector<std::unique_ptr<DAGNode>>& dag, const std::string& bb_name);
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private:
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static const std::vector<PhysicalReg> allocable_regs;
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std::map<Value*, std::string> value_vreg_map; // Maps IR Value* to its virtual register name
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Module* module;
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int vreg_counter = 0; // Counter for unique virtual register names
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int alloca_offset_counter = 0; // Counter for alloca offsets
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};
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} // namespace sysy
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#endif // RISCV32_BACKEND_H
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