gh0s7/xv6-labs
1
1
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

trapslab initialized

Browse Source
This commit is contained in:
CGH0S7
2025-06-12 10:45:04 +08:00
parent 2a8fad821b
commit 028cf61d61
40 changed files with 366 additions and 3188 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
kernel/riscv.h
View File

@ -204,7 +204,7 @@ r_menvcfg()
static inline void
w_menvcfg(uint64 x)
{
//asm volatile("csrw menvcfg, %0" : : "r" (x));
// asm volatile("csrw menvcfg, %0" : : "r" (x));
asm volatile("csrw 0x30a, %0" : : "r" (x));
}
@ -314,14 +314,6 @@ r_sp()
return x;
}
static inline uint64
r_fp()
{
uint64 x;
asm volatile("mv %0, s0" : "=r" (x) );
return x;
}
// read and write tp, the thread pointer, which xv6 uses to hold
// this core's hartid (core number), the index into cpus[].
static inline uint64
@ -362,11 +354,6 @@ typedef uint64 *pagetable_t; // 512 PTEs
#define PGSIZE 4096 // bytes per page
#define PGSHIFT 12 // bits of offset within a page
#ifdef LAB_PGTBL
#define SUPERPGSIZE (2 * (1 << 20)) // bytes per page
#define SUPERPGROUNDUP(sz) (((sz)+SUPERPGSIZE-1) & ~(SUPERPGSIZE-1))
#endif
#define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1))
#define PGROUNDDOWN(a) (((a)) & ~(PGSIZE-1))
@ -375,14 +362,6 @@ typedef uint64 *pagetable_t; // 512 PTEs
#define PTE_W (1L << 2)
#define PTE_X (1L << 3)
#define PTE_U (1L << 4) // user can access
#define PTE_A (1L << 6) // Accessed bit
#define PTE_D (1L << 7) // Dirty bit
#define PTE_PS (1L << 8) // Page Size bit in PTE (for 2MB superpages)
#if defined(LAB_MMAP) || defined(LAB_PGTBL)
#define PTE_LEAF(pte) (((pte) & PTE_R) | ((pte) & PTE_W) | ((pte) & PTE_X))
#endif
// shift a physical address to the right place for a PTE.
#define PA2PTE(pa) ((((uint64)pa) >> 12) << 10)