392 lines
7.3 KiB
C
392 lines
7.3 KiB
C
#ifndef __ASSEMBLER__
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// which hart (core) is this?
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static inline uint64
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r_mhartid()
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{
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uint64 x;
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asm volatile("csrr %0, mhartid" : "=r" (x) );
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return x;
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}
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// Machine Status Register, mstatus
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#define MSTATUS_MPP_MASK (3L << 11) // previous mode.
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#define MSTATUS_MPP_M (3L << 11)
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#define MSTATUS_MPP_S (1L << 11)
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#define MSTATUS_MPP_U (0L << 11)
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#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable.
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static inline uint64
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r_mstatus()
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{
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uint64 x;
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asm volatile("csrr %0, mstatus" : "=r" (x) );
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return x;
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}
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static inline void
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w_mstatus(uint64 x)
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{
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asm volatile("csrw mstatus, %0" : : "r" (x));
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}
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// machine exception program counter, holds the
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// instruction address to which a return from
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// exception will go.
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static inline void
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w_mepc(uint64 x)
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{
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asm volatile("csrw mepc, %0" : : "r" (x));
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}
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// Supervisor Status Register, sstatus
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#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User
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#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable
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#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable
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#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable
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#define SSTATUS_UIE (1L << 0) // User Interrupt Enable
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static inline uint64
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r_sstatus()
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{
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uint64 x;
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asm volatile("csrr %0, sstatus" : "=r" (x) );
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return x;
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}
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static inline void
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w_sstatus(uint64 x)
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{
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asm volatile("csrw sstatus, %0" : : "r" (x));
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}
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// Supervisor Interrupt Pending
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static inline uint64
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r_sip()
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{
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uint64 x;
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asm volatile("csrr %0, sip" : "=r" (x) );
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return x;
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}
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static inline void
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w_sip(uint64 x)
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{
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asm volatile("csrw sip, %0" : : "r" (x));
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}
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// Supervisor Interrupt Enable
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#define SIE_SEIE (1L << 9) // external
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#define SIE_STIE (1L << 5) // timer
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#define SIE_SSIE (1L << 1) // software
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static inline uint64
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r_sie()
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{
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uint64 x;
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asm volatile("csrr %0, sie" : "=r" (x) );
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return x;
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}
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static inline void
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w_sie(uint64 x)
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{
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asm volatile("csrw sie, %0" : : "r" (x));
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}
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// Machine-mode Interrupt Enable
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#define MIE_STIE (1L << 5) // supervisor timer
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static inline uint64
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r_mie()
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{
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uint64 x;
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asm volatile("csrr %0, mie" : "=r" (x) );
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return x;
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}
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static inline void
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w_mie(uint64 x)
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{
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asm volatile("csrw mie, %0" : : "r" (x));
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}
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// supervisor exception program counter, holds the
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// instruction address to which a return from
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// exception will go.
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static inline void
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w_sepc(uint64 x)
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{
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asm volatile("csrw sepc, %0" : : "r" (x));
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}
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static inline uint64
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r_sepc()
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{
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uint64 x;
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asm volatile("csrr %0, sepc" : "=r" (x) );
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return x;
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}
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// Machine Exception Delegation
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static inline uint64
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r_medeleg()
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{
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uint64 x;
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asm volatile("csrr %0, medeleg" : "=r" (x) );
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return x;
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}
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static inline void
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w_medeleg(uint64 x)
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{
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asm volatile("csrw medeleg, %0" : : "r" (x));
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}
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// Machine Interrupt Delegation
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static inline uint64
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r_mideleg()
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{
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uint64 x;
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asm volatile("csrr %0, mideleg" : "=r" (x) );
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return x;
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}
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static inline void
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w_mideleg(uint64 x)
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{
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asm volatile("csrw mideleg, %0" : : "r" (x));
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}
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// Supervisor Trap-Vector Base Address
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// low two bits are mode.
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static inline void
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w_stvec(uint64 x)
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{
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asm volatile("csrw stvec, %0" : : "r" (x));
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}
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static inline uint64
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r_stvec()
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{
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uint64 x;
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asm volatile("csrr %0, stvec" : "=r" (x) );
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return x;
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}
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// Supervisor Timer Comparison Register
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static inline uint64
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r_stimecmp()
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{
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uint64 x;
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// asm volatile("csrr %0, stimecmp" : "=r" (x) );
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asm volatile("csrr %0, 0x14d" : "=r" (x) );
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return x;
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}
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static inline void
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w_stimecmp(uint64 x)
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{
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// asm volatile("csrw stimecmp, %0" : : "r" (x));
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asm volatile("csrw 0x14d, %0" : : "r" (x));
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}
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// Machine Environment Configuration Register
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static inline uint64
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r_menvcfg()
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{
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uint64 x;
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// asm volatile("csrr %0, menvcfg" : "=r" (x) );
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asm volatile("csrr %0, 0x30a" : "=r" (x) );
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return x;
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}
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static inline void
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w_menvcfg(uint64 x)
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{
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// asm volatile("csrw menvcfg, %0" : : "r" (x));
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asm volatile("csrw 0x30a, %0" : : "r" (x));
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}
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// Physical Memory Protection
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static inline void
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w_pmpcfg0(uint64 x)
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{
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asm volatile("csrw pmpcfg0, %0" : : "r" (x));
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}
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static inline void
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w_pmpaddr0(uint64 x)
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{
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asm volatile("csrw pmpaddr0, %0" : : "r" (x));
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}
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// use riscv's sv39 page table scheme.
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#define SATP_SV39 (8L << 60)
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#define MAKE_SATP(pagetable) (SATP_SV39 | (((uint64)pagetable) >> 12))
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// supervisor address translation and protection;
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// holds the address of the page table.
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static inline void
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w_satp(uint64 x)
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{
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asm volatile("csrw satp, %0" : : "r" (x));
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}
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static inline uint64
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r_satp()
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{
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uint64 x;
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asm volatile("csrr %0, satp" : "=r" (x) );
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return x;
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}
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// Supervisor Trap Cause
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static inline uint64
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r_scause()
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{
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uint64 x;
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asm volatile("csrr %0, scause" : "=r" (x) );
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return x;
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}
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// Supervisor Trap Value
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static inline uint64
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r_stval()
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{
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uint64 x;
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asm volatile("csrr %0, stval" : "=r" (x) );
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return x;
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}
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// Machine-mode Counter-Enable
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static inline void
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w_mcounteren(uint64 x)
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{
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asm volatile("csrw mcounteren, %0" : : "r" (x));
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}
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static inline uint64
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r_mcounteren()
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{
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uint64 x;
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asm volatile("csrr %0, mcounteren" : "=r" (x) );
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return x;
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}
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// machine-mode cycle counter
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static inline uint64
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r_time()
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{
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uint64 x;
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asm volatile("csrr %0, time" : "=r" (x) );
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return x;
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}
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// enable device interrupts
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static inline void
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intr_on()
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{
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w_sstatus(r_sstatus() | SSTATUS_SIE);
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}
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// disable device interrupts
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static inline void
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intr_off()
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{
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w_sstatus(r_sstatus() & ~SSTATUS_SIE);
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}
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// are device interrupts enabled?
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static inline int
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intr_get()
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{
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uint64 x = r_sstatus();
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return (x & SSTATUS_SIE) != 0;
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}
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static inline uint64
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r_sp()
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{
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uint64 x;
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asm volatile("mv %0, sp" : "=r" (x) );
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return x;
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}
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// read and write tp, the thread pointer, which xv6 uses to hold
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// this core's hartid (core number), the index into cpus[].
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static inline uint64
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r_tp()
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{
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uint64 x;
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asm volatile("mv %0, tp" : "=r" (x) );
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return x;
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}
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static inline void
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w_tp(uint64 x)
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{
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asm volatile("mv tp, %0" : : "r" (x));
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}
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static inline uint64
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r_ra()
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{
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uint64 x;
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asm volatile("mv %0, ra" : "=r" (x) );
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return x;
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}
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// 读取当前帧指针（s0）寄存器的值
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static inline uint64
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r_fp()
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{
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uint64 x;
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asm volatile("mv %0, s0" : "=r" (x) );
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return x;
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}
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// flush the TLB.
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static inline void
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sfence_vma()
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{
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// the zero, zero means flush all TLB entries.
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asm volatile("sfence.vma zero, zero");
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}
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typedef uint64 pte_t;
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typedef uint64 *pagetable_t; // 512 PTEs
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#endif // __ASSEMBLER__
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#define PGSIZE 4096 // bytes per page
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#define PGSHIFT 12 // bits of offset within a page
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#define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1))
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#define PGROUNDDOWN(a) (((a)) & ~(PGSIZE-1))
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#define PTE_V (1L << 0) // valid
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#define PTE_R (1L << 1)
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#define PTE_W (1L << 2)
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#define PTE_X (1L << 3)
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#define PTE_U (1L << 4) // user can access
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// shift a physical address to the right place for a PTE.
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#define PA2PTE(pa) ((((uint64)pa) >> 12) << 10)
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#define PTE2PA(pte) (((pte) >> 10) << 12)
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#define PTE_FLAGS(pte) ((pte) & 0x3FF)
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// extract the three 9-bit page table indices from a virtual address.
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#define PXMASK 0x1FF // 9 bits
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#define PXSHIFT(level) (PGSHIFT+(9*(level)))
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#define PX(level, va) ((((uint64) (va)) >> PXSHIFT(level)) & PXMASK)
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// one beyond the highest possible virtual address.
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// MAXVA is actually one bit less than the max allowed by
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// Sv39, to avoid having to sign-extend virtual addresses
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// that have the high bit set.
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#define MAXVA (1L << (9 + 9 + 9 + 12 - 1))
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