# Override configurations in ../example-sky130.yml and example-designs

# Specify clock signals
# Rocket/RocketTile names clock signal "clock" instead of "clock_clock"
vlsi.inputs.clocks: [
  {name: "clock", period: "30ns", uncertainty: "3ns"}
]

# Placement Constraints
# Placement Constraints
vlsi.inputs.placement_constraints:
  - path: "RocketTile"
    type: toplevel
    x: 0
    y: 0
    width: 4000
    height: 3000
    margins:
      left: 10
      right: 0
      top: 10
      bottom: 10

  # Place SRAM memory instances
  # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
  # data cache
  - path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 50
    orientation: r90
  - path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 450
    orientation: r90
  - path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 850
    orientation: r90
  - path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 1250
    orientation: r90
 
  # tag array
  - path: "RocketTile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 1600
    orientation: r90

  # instruction cache
  - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 2100
    orientation: r90
