From e8f89d228ceb4e4c6311648a654157265898cf33 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 18 Dec 2023 09:31:42 -0800 Subject: [PATCH 1/7] Move CIRCT install to its own step in build-setup script --- scripts/build-setup.sh | 38 ++++++++++++++++++++++++++------------ 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh index 9d79735a..d3a66ca6 100755 --- a/scripts/build-setup.sh +++ b/scripts/build-setup.sh @@ -29,7 +29,8 @@ usage() { echo " 7. FireSim pre-compile sources" echo " 8. FireMarshal" echo " 9. FireMarshal pre-compile default buildroot Linux sources" - echo " 10. Runs repository clean-up" + echo " 10. Install CIRCT" + echo " 11. Runs repository clean-up" echo "" echo "**See below for options to skip parts of the setup. Skipping parts of the setup is not guaranteed to be tested/working.**" echo "" @@ -152,16 +153,6 @@ if run_step "1"; then conda activate $CYDIR/.conda-env exit_if_last_command_failed - # install circt into conda - git submodule update --init $CYDIR/tools/install-circt && - $CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \ - -f circt-full-shared-linux-x64.tar.gz \ - -i $CONDA_PREFIX \ - -v version-file \ - -x $CYDIR/conda-reqs/circt.json \ - -g null - exit_if_last_command_failed - # Conda Setup # Provide a sourceable snippet that can be used in subshells that may not have # inhereted conda functions that would be brought in under a login shell that @@ -273,8 +264,31 @@ if run_step "8"; then popd fi -# do misc. cleanup for a "clean" git status if run_step "10"; then + # install circt into conda + if run_step "1"; then + PREFIX=$CONDA_PREFIX/$TOOLCHAIN_TYPE + else + if [ -z "$RISCV" ] ; then + error "ERROR: If conda initialization skipped, \$RISCV variable must be defined." + exit 1 + fi + PREFIX=$RISCV + fi + + git submodule update --init $CYDIR/tools/install-circt && + $CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \ + -f circt-full-shared-linux-x64.tar.gz \ + -i $PREFIX \ + -v version-file \ + -x $CYDIR/conda-reqs/circt.json \ + -g null + exit_if_last_command_failed +fi + + +# do misc. cleanup for a "clean" git status +if run_step "11"; then begin_step "10" "Cleaning up repository" $CYDIR/scripts/repo-clean.sh exit_if_last_command_failed From 81a2857ec77a93c424012e7a5f1d98ba896cbc5f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 19 Dec 2023 15:45:20 -0800 Subject: [PATCH 2/7] Add arty100t harness binder to map UART to PMOD JD --- fpga/src/main/scala/arty100t/Configs.scala | 4 ++- fpga/src/main/scala/arty100t/Harness.scala | 3 -- .../main/scala/arty100t/HarnessBinders.scala | 33 ++++++++++++++++++- 3 files changed, 35 insertions(+), 5 deletions(-) diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index 213425f5..fce9177d 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -21,7 +21,10 @@ class WithNoDesignKey extends Config((site, here, up) => { case DesignKey => (p: Parameters) => new SimpleLazyModule()(p) }) +// By default, this uses the on-board USB-UART for the TSI-over-UART link +// The PMODUART HarnessBinder maps the actual UART device to JD pin class WithArty100TTweaks(freqMHz: Double = 50) extends Config( + new WithArty100TPMODUART ++ new WithArty100TUARTTSI ++ new WithArty100TDDRTL ++ new WithNoDesignKey ++ @@ -37,7 +40,6 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config( new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.config.WithNoDebug ++ // no jtag - new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY new freechips.rocketchip.subsystem.WithoutTLMonitors) diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala index a535e65f..577bd1b2 100644 --- a/fpga/src/main/scala/arty100t/Harness.scala +++ b/fpga/src/main/scala/arty100t/Harness.scala @@ -33,9 +33,6 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell harnessSysPLLNode := clockOverlay.overlayOutput.node - val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0)))) - val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) - val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay] val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( name = "chip_ddr", diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index 4c821970..6ad8defd 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -25,7 +25,17 @@ import testchipip._ class WithArty100TUARTTSI extends HarnessBinder({ case (th: HasHarnessInstantiators, port: UARTTSIPort) => { val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] - ath.io_uart_bb.bundle <> port.io.uart + val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart_tsi") + harnessIO <> port.io + val packagePinsWithPackageIOs = Seq( + ("A9" , IOPin(harnessIO.uart.rxd)), + ("D10", IOPin(harnessIO.uart.txd))) + packagePinsWithPackageIOs foreach { case (pin, io) => { + ath.xdc.addPackagePin(io, pin) + ath.xdc.addIOStandard(io, "LVCMOS33") + ath.xdc.addIOB(io) + } } + ath.other_leds(1) := port.io.dropped ath.other_leds(9) := port.io.tsi2tl_state(0) ath.other_leds(10) := port.io.tsi2tl_state(1) @@ -34,6 +44,7 @@ class WithArty100TUARTTSI extends HarnessBinder({ } }) + class WithArty100TDDRTL extends HarnessBinder({ case (th: HasHarnessInstantiators, port: TLMemPort) => { val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] @@ -83,3 +94,23 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({ artyTh.xdc.clockDedicatedRouteFalse(clkIO) } }) + +// Maps the UART device to the on-board USB-UART +class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: UARTPort) => { + val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] + val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart") + harnessIO <> port.io + val packagePinsWithPackageIOs = Seq( + (rxdPin, IOPin(harnessIO.rxd)), + (txdPin, IOPin(harnessIO.txd))) + packagePinsWithPackageIOs foreach { case (pin, io) => { + ath.xdc.addPackagePin(io, pin) + ath.xdc.addIOStandard(io, "LVCMOS33") + ath.xdc.addIOB(io) + } } + } +}) + +// Maps the UART device to PMOD JD pins 3/7 +class WithArty100TPMODUART extends WithArty100TUART("E2", "F4") From 902d33ebd1448ef80c6596b8ffe887a8e8b412ed Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 20 Dec 2023 08:43:35 -0800 Subject: [PATCH 3/7] Add Arty100T JTAG --- fpga/src/main/scala/arty100t/Configs.scala | 2 +- .../main/scala/arty100t/HarnessBinders.scala | 25 ++++++++++++++++++- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index fce9177d..df29d5af 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -27,6 +27,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config( new WithArty100TPMODUART ++ new WithArty100TUARTTSI ++ new WithArty100TDDRTL ++ + new WithArty100TJTAG ++ new WithNoDesignKey ++ new testchipip.WithUARTTSIClient ++ new chipyard.harness.WithSerialTLTiedOff ++ @@ -39,7 +40,6 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config( new chipyard.config.WithOffchipBusFrequency(freqMHz) ++ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.clocking.WithPassthroughClockGenerator ++ - new chipyard.config.WithNoDebug ++ // no jtag new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY new freechips.rocketchip.subsystem.WithoutTLMonitors) diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index 6ad8defd..64676584 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -113,4 +113,27 @@ class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends Ha }) // Maps the UART device to PMOD JD pins 3/7 -class WithArty100TPMODUART extends WithArty100TUART("E2", "F4") +class WithArty100TPMODUART extends WithArty100TUART("G2", "F3") + +class WithArty100TJTAG extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: JTAGPort) => { + val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] + val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag") + harnessIO <> port.io + + ath.sdc.addClock("JTCK", IOPin(harnessIO.TCK), 10) + ath.sdc.addGroup(clocks = Seq("JTCK")) + ath.xdc.clockDedicatedRouteFalse(IOPin(harnessIO.TCK)) + val packagePinsWithPackageIOs = Seq( + ("F4", IOPin(harnessIO.TCK)), + ("D2", IOPin(harnessIO.TMS)), + ("E2", IOPin(harnessIO.TDI)), + ("D4", IOPin(harnessIO.TDO)) + ) + packagePinsWithPackageIOs foreach { case (pin, io) => { + ath.xdc.addPackagePin(io, pin) + ath.xdc.addIOStandard(io, "LVCMOS33") + ath.xdc.addPullup(io) + } } + } +}) From 77c3b65fc93b23fd6336858b55b3b20297eaefd7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 26 Dec 2023 09:39:08 -0800 Subject: [PATCH 4/7] Don't punch out uart2tsi debug io --- fpga/src/main/scala/arty100t/HarnessBinders.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index 64676584..bbb966bb 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -25,11 +25,11 @@ import testchipip._ class WithArty100TUARTTSI extends HarnessBinder({ case (th: HasHarnessInstantiators, port: UARTTSIPort) => { val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] - val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart_tsi") - harnessIO <> port.io + val harnessIO = IO(new UARTPortIO(port.io.uartParams)).suggestName("uart_tsi") + harnessIO <> port.io.uart val packagePinsWithPackageIOs = Seq( - ("A9" , IOPin(harnessIO.uart.rxd)), - ("D10", IOPin(harnessIO.uart.txd))) + ("A9" , IOPin(harnessIO.rxd)), + ("D10", IOPin(harnessIO.txd))) packagePinsWithPackageIOs foreach { case (pin, io) => { ath.xdc.addPackagePin(io, pin) ath.xdc.addIOStandard(io, "LVCMOS33") From 81fd8edb066124ea1c5cb0286b269c68e37f5ac9 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 29 Dec 2023 15:35:35 -0800 Subject: [PATCH 5/7] ADD: add scratchpad --- fpga/src/main/scala/arty100t/Configs.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index d5c83af3..03ab2b1e 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -46,6 +46,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config( class RocketArty100TConfig extends Config( new WithArty100TTweaks ++ + new testchipip.soc.WithMbusScratchpad(base = 0x08000000, size = 128 * 1024) ++ // use rocket l1 DCache scratchpad as base phys mem new chipyard.config.WithBroadcastManager ++ // no l2 new chipyard.RocketConfig) From 0ba5c62b30fb50f4e87331c3c7942909a0053def Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 29 Dec 2023 16:15:59 -0800 Subject: [PATCH 6/7] FIX: fix scratchpad description --- fpga/src/main/scala/arty100t/Configs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index 03ab2b1e..140df42b 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -46,7 +46,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config( class RocketArty100TConfig extends Config( new WithArty100TTweaks ++ - new testchipip.soc.WithMbusScratchpad(base = 0x08000000, size = 128 * 1024) ++ // use rocket l1 DCache scratchpad as base phys mem + new testchipip.soc.WithMbusScratchpad(base = 0x08000000, size = 128 * 1024) ++ // add on-chip scratchpad for small programs new chipyard.config.WithBroadcastManager ++ // no l2 new chipyard.RocketConfig) From c2175f45004d5aab5d7384419c751b513f1af397 Mon Sep 17 00:00:00 2001 From: Tynan McAuley Date: Fri, 29 Dec 2023 21:22:34 -0800 Subject: [PATCH 7/7] Reduce CDE lookups for IOBinders --- generators/chipyard/src/main/scala/iobinders/IOBinders.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 45f72641..7695be70 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -116,7 +116,10 @@ object GetSystemParameters { } class IOBinder[T](composer: Seq[IOBinderFunction] => Seq[IOBinderFunction])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { - case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> composer(up(IOBinders, site)(tag.runtimeClass.toString))) + case IOBinders => { + val upMap = up(IOBinders) + upMap + (tag.runtimeClass.toString -> composer(upMap(tag.runtimeClass.toString))) + } }) class ConcreteIOBinder[T](composes: Boolean, fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends IOBinder[T](