Rename Config Mixins to Fragments (#451)

* [docs] rename config mixins -> fragments [ci skip]

* [docs] cleanup naming | link similar sections [ci skip]

* [boom] bump for mixin rename [ci skip]

* [docs] cleanup capitalization [ci skip]

* [docs] consistent config fragment naming [ci skip]

* [boom] bump boom for documentation changes [ci skip]

* [docs] update source comments [ci skip]

* [docs] fix last config fragment name [ci skip]

Co-Authored-By: alonamid <alonamid@eecs.berkeley.edu>

Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -32,7 +32,7 @@ object ConfigValName {
 import ConfigValName._
 
 // -----------------------
-// Common Parameter Mixins
+// Common Config Fragments
 // -----------------------
 
 class WithBootROM extends Config((site, here, up) => {
@@ -40,12 +40,12 @@ class WithBootROM extends Config((site, here, up) => {
     contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
 })
 
-// DOC include start: gpio mixin
+// DOC include start: gpio config fragment
 class WithGPIO extends Config((site, here, up) => {
   case PeripheryGPIOKey => Seq(
     GPIOParams(address = 0x10012000, width = 4, includeIOF = false))
 })
-// DOC include end: gpio mixin
+// DOC include end: gpio config fragment
 
 class WithUART extends Config((site, here, up) => {
   case PeripheryUARTKey => Seq(
@@ -80,14 +80,14 @@ class WithTracegenTop extends Config((site, here, up) => {
 case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]])
 
 /**
- * Mixin to enable different RoCCs based on the hartId
+ * Config fragment to enable different RoCCs based on the hartId
  */
 class WithMultiRoCC extends Config((site, here, up) => {
   case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil)
 })
 
 /**
- * Mixin to add Hwachas to cores based on hart
+ * Config fragment to add Hwachas to cores based on hart
  *
  * For ex:
  *   Core 0, 1, 2, 3 have been defined earlier
@@ -110,7 +110,7 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
 
 
 /**
- * Mixin to add a small Rocket core to the system as a "control" core.
+ * Config fragment to add a small Rocket core to the system as a "control" core.
  * Used as an example of a PMU core.
  */
 class WithControlCore extends Config((site, here, up) => {

generators/chipyard/src/main/scala/GCD.scala

@@ -200,8 +200,8 @@ trait CanHavePeripheryGCDModuleImp extends LazyModuleImp {
 // DOC include end: GCD imp trait
 
 
-// DOC include start: GCD mixin
+// DOC include start: GCD config fragment
 class WithGCD(useAXI4: Boolean, useBlackBox: Boolean) extends Config((site, here, up) => {
   case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox))
 })
-// DOC include end: GCD mixin
+// DOC include end: GCD config fragment