From a3a05ec9881144ba3535adb06ea81de04109f8d2 Mon Sep 17 00:00:00 2001 From: Brendan Sweeney Date: Wed, 25 Sep 2019 13:45:21 -0700 Subject: [PATCH 1/3] [docs] [ci skip] Update generators and quick start so it is clear how to edit the generators to get changed outputs (You just edit the source) --- docs/Generators/index.rst | 8 +++++++- docs/Quick-Start.rst | 2 ++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index a01b5adc..8bd17024 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -1,12 +1,18 @@ +.. _generator-index: + Generators ============================ -Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL. +A Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL. This type of meta-programming is enabled by the Chisel hardware description language (see :ref:`Chisel`). A standard RTL design is essentially just a single instance of a design coming from a generator. However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways. The following pages introduce the generators integrated with the Chipyard framework. +Chipyard bundles the source code for the generators, under the ``generators`` directory. +It builds them from source each time (although ``sbt`` will cache results if they have not changed), +so changes to the generators themselves will automatically be used when building with Chipyard. + .. toctree:: :maxdepth: 2 :caption: Generators: diff --git a/docs/Quick-Start.rst b/docs/Quick-Start.rst index 86d62b11..8d45e436 100644 --- a/docs/Quick-Start.rst +++ b/docs/Quick-Start.rst @@ -52,3 +52,5 @@ This depends on what you are planning to do with Chipyard. * To run a FPGA-accelerated simulation using FireSim, see :ref:`firesim-sim-intro`. * To run a VLSI flow using one of the vanilla Chipyard examples, see <>. + +* To change the generators (BOOM, Rocket, &c) themselves, see :ref:`generator-index`. From e8a197d8a85f8d9e43b451b5c37c6c1e7eda619b Mon Sep 17 00:00:00 2001 From: Brendan Sweeney Date: Wed, 25 Sep 2019 17:18:27 -0700 Subject: [PATCH 2/3] [docs] [ci skip] --- docs/Generators/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 8bd17024..0e120e45 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -10,7 +10,7 @@ However, by using meta-programming and parameter systems, generators can allow f The following pages introduce the generators integrated with the Chipyard framework. Chipyard bundles the source code for the generators, under the ``generators`` directory. -It builds them from source each time (although ``sbt`` will cache results if they have not changed), +It builds them from source each time (although the build system will cache results if they have not changed), so changes to the generators themselves will automatically be used when building with Chipyard. .. toctree:: From c4c8cc65afb5bb68d8ab8a28a8949191c4c10151 Mon Sep 17 00:00:00 2001 From: Brendan Sweeney Date: Wed, 25 Sep 2019 17:56:16 -0700 Subject: [PATCH 3/3] [docs] [ci skip] Alon's comments --- docs/Generators/index.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 0e120e45..b93a3681 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -11,7 +11,8 @@ The following pages introduce the generators integrated with the Chipyard framew Chipyard bundles the source code for the generators, under the ``generators`` directory. It builds them from source each time (although the build system will cache results if they have not changed), -so changes to the generators themselves will automatically be used when building with Chipyard. +so changes to the generators themselves will automatically be used when building with Chipyard and propagate to software simulation, FPGA-accelerated simulation, and VLSI flows. + .. toctree:: :maxdepth: 2