From 02eedb898c321964d08bbe1373e696368b906d1a Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Thu, 27 Jun 2024 17:18:09 -0700
Subject: [PATCH] Fix module imports after rocket-chip bump

---
 .../chipyard/src/main/scala/config/CoalescerConfigs.scala      | 2 +-
 .../chipyard/src/main/scala/config/RadianceConfigs.scala       | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala
index 58456bdd..c88d1635 100644
--- a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala
@@ -1,7 +1,7 @@
 package chipyard
 
 import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
+import freechips.rocketchip.prci.AsynchronousCrossing
 
 class MemtraceCoreConfig extends Config(
   // Memtrace
diff --git a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala
index 0cbaed5a..8938f057 100644
--- a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala
@@ -3,7 +3,8 @@ package chipyard
 import chipyard.config.AbstractConfig
 import chipyard.stage.phases.TargetDirKey
 import freechips.rocketchip.devices.tilelink.BootROMLocated
-import freechips.rocketchip.diplomacy.{AsynchronousCrossing, BigIntHexContext}
+import freechips.rocketchip.prci.AsynchronousCrossing
+import freechips.rocketchip.resources.BigIntHexContext
 import freechips.rocketchip.subsystem._
 import org.chipsalliance.cde.config.Config
 import radiance.memory._