Merge pull request #1237 from ucb-bar/harrisonliew-patch-1
This commit is contained in:
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CHANGELOG.md
10
CHANGELOG.md
@@ -9,9 +9,10 @@ Adds support for NoC-based interconnects with Constellation (https://constellati
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### Added
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### Added
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* RTL: Support for packet-switched NoC-based TileLink main bus interconnects with Constellation
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* RTL: Support for packet-switched NoC-based TileLink main bus interconnects with Constellation
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* Conda: Support setting up a Chipyard development environment through Conda
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* Conda: Support setting up a Chipyard development environment through Conda
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* Hammer: Fully open-source Sky130 flow with Yosys, OpenROAD, Magic, Netgen
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* Hammer: Fully open-source Sky130 flow tutorials in open-source and commercial tools
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* Hammer: VCS FGP (fine-grained parallelism) support
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* Hammer: IR key history
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* Hammer: Support for Conformal LEC
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* Hammer: Joules power analysis support
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* Hammer: Tempus STA support
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### Changed
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### Changed
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* RTL: Default memory-mapped addresses for fft/dsp/example MMIO accelerators changed to be non-overlapping
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* RTL: Default memory-mapped addresses for fft/dsp/example MMIO accelerators changed to be non-overlapping
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@@ -23,8 +24,7 @@ Adds support for NoC-based interconnects with Constellation (https://constellati
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### Fixed
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### Fixed
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* RTL: Fix clock frequency rounding
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* RTL: Fix clock frequency rounding
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* Hammer: FSDB support for Cadence Voltus
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* Hammer: VCS FGP is now opt-in
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* Hammer: Various fixes to ASAP7 dummy SRAMs
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* Dromajo: Fix to variable definition
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* Dromajo: Fix to variable definition
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* Testchipip: Fix write-strobe handling for 64B configurations
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* Testchipip: Fix write-strobe handling for 64B configurations
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* Build: Ignore dotfiles in lookup_srcs
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* Build: Ignore dotfiles in lookup_srcs
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