diff --git a/build.sbt b/build.sbt index 5e559893..802dabf6 100644 --- a/build.sbt +++ b/build.sbt @@ -60,7 +60,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => new Group(test.name, Seq(test), SubProcess(options)) } toSeq -val chiselVersion = "3.5.1" +val chiselVersion = "3.5.2" lazy val chiselSettings = Seq( libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion, diff --git a/fpga/fpga-shells b/fpga/fpga-shells index f9fb9fd3..60adb8c6 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit f9fb9fd338e5fca2ff5116b1d01506c424280d70 +Subproject commit 60adb8c62c81c57b7eabd0402d9505c0ea1545f9 diff --git a/generators/boom b/generators/boom index ad64c541..fac2c370 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit ad64c5419151e5e886daee7084d8399713b46b4b +Subproject commit fac2c370c9deae97ca52aca6b34857e9ac0f6e9d diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala deleted file mode 100644 index 7bbd53f1..00000000 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ /dev/null @@ -1,82 +0,0 @@ - -package chipyard - -import freechips.rocketchip.config.{Field, Config, Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util.{Location, Symmetric} -import freechips.rocketchip.subsystem._ - -// I'm putting this code here temporarily as I think it should be a candidate -// for upstreaming based on input from Henry Cook, but don't wnat to deal with -// an RC branch just yet. - -// For subsystem/BusTopology.scala - -// Biancolin: This, modified from Henry's email -/** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */ -case class CoherentMulticlockBusTopologyParams( - sbus: SystemBusParams, // TODO remove this after better width propagation - mbus: MemoryBusParams, - l2: BankedL2Params, - sbusToMbusXType: ClockCrossingType = NoCrossing -) extends TLBusWrapperTopology( - instantiations = (if (l2.nBanks == 0) Nil else List( - (MBUS, mbus), - (L2, CoherenceManagerWrapperParams(mbus.blockBytes, mbus.beatBytes, l2.nBanks, L2.name)(l2.coherenceManager)))), - connections = if (l2.nBanks == 0) Nil else List( - (SBUS, L2, TLBusWrapperConnection(xType = NoCrossing, driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()), - (L2, MBUS, TLBusWrapperConnection.crossTo( - xType = sbusToMbusXType, - driveClockFromMaster = None, - nodeBinding = BIND_QUERY)) - ) -) - -// This differs from upstream only in that it does not use the legacy crossTo -// and crossFrom functions, and it ensures driveClockFromMaster = None -case class HierarchicalMulticlockBusTopologyParams( - pbus: PeripheryBusParams, - fbus: FrontBusParams, - cbus: PeripheryBusParams, - xTypes: SubsystemCrossingParams -) extends TLBusWrapperTopology( - instantiations = List( - (PBUS, pbus), - (FBUS, fbus), - (CBUS, cbus)), - connections = List( - (SBUS, CBUS, TLBusWrapperConnection. crossTo(xType = xTypes.sbusToCbusXType, driveClockFromMaster = None)), - (CBUS, PBUS, TLBusWrapperConnection. crossTo(xType = xTypes.cbusToPbusXType, driveClockFromMaster = None)), - (FBUS, SBUS, TLBusWrapperConnection.crossFrom(xType = xTypes.fbusToSbusXType, driveClockFromMaster = None))) -) - -// For subsystem/Configs.scala - -class WithMulticlockCoherentBusTopology extends Config((site, here, up) => { - case TLNetworkTopologyLocated(InSubsystem) => List( - JustOneBusTopologyParams(sbus = site(SystemBusKey)), - HierarchicalMulticlockBusTopologyParams( - pbus = site(PeripheryBusKey), - fbus = site(FrontBusKey), - cbus = site(ControlBusKey), - xTypes = SubsystemCrossingParams( - sbusToCbusXType = site(SbusToCbusXTypeKey), - cbusToPbusXType = site(CbusToPbusXTypeKey), - fbusToSbusXType = site(FbusToSbusXTypeKey))), - CoherentMulticlockBusTopologyParams( - sbus = site(SystemBusKey), - mbus = site(MemoryBusKey), - l2 = site(BankedL2Key), - sbusToMbusXType = site(SbusToMbusXTypeKey))) -}) - -class WithMulticlockIncoherentBusTopology extends Config((site, here, up) => { - case TLNetworkTopologyLocated(InSubsystem) => List( - JustOneBusTopologyParams(sbus = site(SystemBusKey)), - HierarchicalMulticlockBusTopologyParams( - pbus = site(PeripheryBusKey), - fbus = site(FrontBusKey), - cbus = site(ControlBusKey), - xTypes = SubsystemCrossingParams())) -}) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 93d7c237..f5e35477 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -13,8 +13,6 @@ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey} import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt} -import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree} import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.interrupts._ diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index 31bedae7..827b97c0 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -60,7 +60,7 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem => private val device = new MemoryDevice private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) - val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) => + val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels, _) => Seq.tabulate(nMemoryChannels) { channel => val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 3cbeb32a..1f43dcbf 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -41,20 +41,21 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithCustomBootPin ++ new chipyard.iobinders.WithDividerOnlyClockGenerator ++ - new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance - new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks - new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set - new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) - new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus - new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus - new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2 - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance + new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks + new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set + new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) + new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus + new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus + new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 0f9b5992..42805714 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -15,7 +15,7 @@ class TinyRocketConfig extends Config( new chipyard.config.WithTLSerialLocation( freechips.rocketchip.subsystem.FBUS, freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses - new chipyard.WithMulticlockIncoherentBusTopology ++ // use incoherent bus topology + new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 97294428..6303e31a 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -7,7 +7,6 @@ import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{LogicalTreeNode} import freechips.rocketchip.rocket._ import freechips.rocketchip.subsystem.{RocketCrossingParams} import freechips.rocketchip.tilelink._ diff --git a/generators/cva6 b/generators/cva6 index 705c48a1..31fd9cdf 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 705c48a1dacc011cef9b4d021a88b4948e7f9b64 +Subproject commit 31fd9cdf801b407acee3989622902db59e474f90 diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 3839bf14..bd35341b 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -262,9 +262,7 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessSigna // instantiation of the dut, otherwise the initial instance will be // reused across each node import freechips.rocketchip.subsystem.AsyncClockGroupsKey - val lazyModule = LazyModule(p(BuildTop)(p.alterPartial({ - case AsyncClockGroupsKey => p(AsyncClockGroupsKey).copy - }))) + val lazyModule = LazyModule(p(BuildTop)(p)) val module = Module(lazyModule.module) lazyModule match { case d: HasIOBinders => diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 5643a8e2..fc56b712 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 5643a8e245d562647f626295ad2dab9b4d5f6a13 +Subproject commit fc56b7128f8d5fd3d9022e19ee53c93e0ecfad05 diff --git a/generators/rocket-chip b/generators/rocket-chip index 114325b2..44b0b824 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 114325b27cfe5312c86a8a325b187be9455a62af +Subproject commit 44b0b8249279d25bd75ea693b725d9ff1b96e2ab diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 545a396f..e8adf0e3 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 545a396f3486132b01ceef3cbce2085608984478 +Subproject commit e8adf0e3ef94f76f73001fbeda767d6899c60eb3 diff --git a/generators/sifive-cache b/generators/sifive-cache index e3a3000c..2e47c707 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit e3a3000cc1fd4cdf3a4e638e4d081b8aae94ebf0 +Subproject commit 2e47c707e04dbbbdbf81561a979c055f87ac8df2 diff --git a/generators/testchipip b/generators/testchipip index eea390af..f99b1eb5 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit eea390af19a05b9d6874c3ec51903d89c5520bf2 +Subproject commit f99b1eb59a34d7934059904f03237d5bc8d4a680