From 0656c5da4f0e99e0be5a4a18626a96c6462f5006 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Sep 2020 20:29:19 -0700 Subject: [PATCH] First pass on using CY make system --- fpga/Makefile | 93 +++++++++++++++++++++++++ fpga/src/main/scala/arty/Config.scala | 4 +- fpga/src/main/scala/arty/Platform.scala | 1 + fpga/src/main/scala/arty/System.scala | 12 +++- 4 files changed, 105 insertions(+), 5 deletions(-) create mode 100644 fpga/Makefile diff --git a/fpga/Makefile b/fpga/Makefile new file mode 100644 index 00000000..dcafb930 --- /dev/null +++ b/fpga/Makefile @@ -0,0 +1,93 @@ +######################################################################################### +# fpga prototype makefile +######################################################################################### + +######################################################################################### +# general path variables +######################################################################################### +base_dir=$(abspath ..) +sim_dir=$(abspath .) + +######################################################################################### +# include shared variables +######################################################################################### +include $(base_dir)/variables.mk + +export SUB_PROJECT=fpga +export SBT_PROJECT=freedomPlatforms +export MODEL=E300ArtyDevKitFPGAChip +export VLOG_MODEL=E300ArtyDevKitFPGAChip +export MODEL_PACKAGE=sifive.freedom.everywhere.e300artydevkit +export CONFIG=E300ArtyDevKitConfig +export CONFIG_PACKAGE=sifive.freedom.everywhere.e300artydevkit +export GENERATOR_PACKAGE=chipyard +export TB=none +export TOP=E300ArtyDevKitPlatform +export BOARD=arty + +export bootrom_dir := $(base_dir)/fpga/bootrom/xip +fpga_dir=$(base_dir)/fpga/fpga-shells/xilinx + +sim_name = verilator # unused + +######################################################################################### +# import other necessary rules and variables +######################################################################################### +include $(base_dir)/common.mk + +######################################################################################### +# copy from other directory +######################################################################################### +romgen := $(build_dir)/$(CONFIG_PROJECT).$(CONFIG).rom.v +$(romgen): $(verilog) +ifneq ($(bootrom_dir),"") + $(MAKE) -C $(bootrom_dir) romgen + mv $(build_dir)/rom.v $@ +endif + +.PHONY: romgen +romgen: $(romgen) + +f := $(build_dir)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F +$(f): + echo $(VSRCS) > $@ + +bit := $(build_dir)/obj/$(MODEL).bit +$(bit): $(romgen) $(f) + cd $(build_dir); vivado \ + -nojournal -mode batch \ + -source $(fpga_common_script_dir)/vivado.tcl \ + -tclargs \ + -top-module "$(MODEL)" \ + -F "$(f)" \ + -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ + -board "$(BOARD)" + + +# Build .mcs +mcs := $(build_dir)/obj/$(MODEL).mcs +$(mcs): $(bit) + cd $(build_dir); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< + +.PHONY: mcs +mcs: $(mcs) + +# Build Libero project +prjx := $(build_dir)/libero/$(MODEL).prjx +$(prjx): $(verilog) + cd $(build_dir); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(build_dir) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)" + +.PHONY: prjx +prjx: $(prjx) + + +######################################################################################### +# general cleanup rules +######################################################################################### +.PHONY: clean +clean: + rm -rf $(gen_dir) +ifneq ($(bootrom_dir),"") + $(MAKE) -C $(bootrom_dir) clean +endif + $(MAKE) -C $(FPGA_DIR) clean diff --git a/fpga/src/main/scala/arty/Config.scala b/fpga/src/main/scala/arty/Config.scala index 45f83036..11642164 100644 --- a/fpga/src/main/scala/arty/Config.scala +++ b/fpga/src/main/scala/arty/Config.scala @@ -47,8 +47,8 @@ class E300DevKitPeripherals extends Config((site, here, up) => { I2CParams(address = 0x10016000)) case PeripheryMockAONKey => MockAONParams(address = 0x10000000) - case PeripheryMaskROMKey => List( - MaskROMParams(address = 0x10000, name = "BootROM")) + case MaskROMLocated(InSubsystem) => List(MaskROMParams(address = 0x10000, name = "BootROM")) + case BootROMLocated(InSubsystem) => None }) // Freedom E300 Arty Dev Kit Peripherals diff --git a/fpga/src/main/scala/arty/Platform.scala b/fpga/src/main/scala/arty/Platform.scala index 0f76cb15..14c31628 100644 --- a/fpga/src/main/scala/arty/Platform.scala +++ b/fpga/src/main/scala/arty/Platform.scala @@ -51,6 +51,7 @@ class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle { //------------------------------------------------------------------------- class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module { + //val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) This can be DigitalTop? val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) val io = new E300ArtyDevKitPlatformIO diff --git a/fpga/src/main/scala/arty/System.scala b/fpga/src/main/scala/arty/System.scala index f614c06c..46e5c34e 100644 --- a/fpga/src/main/scala/arty/System.scala +++ b/fpga/src/main/scala/arty/System.scala @@ -31,6 +31,12 @@ class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem with HasPeripheryGPIO with HasPeripheryPWM with HasPeripheryI2C { + val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } + val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } + + val maskROMResetVectorSourceNode = BundleBridgeSource[UInt]() + tileResetVectorNexusNode := maskROMResetVectorSourceNode + override lazy val module = new E300ArtyDevKitSystemModule(this) } @@ -45,7 +51,7 @@ class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L) with HasPeripheryMockAONModuleImp with HasPeripheryPWMModuleImp with HasPeripheryI2CModuleImp { - // Reset vector is set to the location of the mask rom - val maskROMParams = p(PeripheryMaskROMKey) - global_reset_vector := maskROMParams(0).address.U + + // connect reset vector to 1st MaskROM + _outer.maskROMResetVectorSourceNode.bundle := p(MaskROMLocated(_outer.location))(0).address.U }