diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala
index 6bf72343..f39661af 100644
--- a/generators/chipyard/src/main/scala/example/InitZero.scala
+++ b/generators/chipyard/src/main/scala/example/InitZero.scala
@@ -61,8 +61,8 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem =>
   implicit val p: Parameters
 
   p(InitZeroKey) .map { k =>
-    val initZero = LazyModule(new InitZero()(p))
     val fbus = locateTLBusWrapper(FBUS)
+    val initZero = fbus { LazyModule(new InitZero()(p)) }
     fbus.coupleFrom("init-zero") { _ := initZero.node }
   }
 }