From 07e19e5bb80f5fff0f5feb05c910c3515c06b782 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 17 Apr 2023 11:56:12 -0700 Subject: [PATCH] Increase debug module data capacity --- .../chipyard/src/main/scala/config/AbstractConfig.scala | 1 + .../src/main/scala/config/fragments/PeripheralFragments.scala | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 5611dad5..ef02f468 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -48,6 +48,7 @@ class AbstractConfig extends Config( new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM + new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 7ac7f569..56cd3bb6 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -87,3 +87,7 @@ class WithExtMemIdBits(n: Int) extends Config((site, here, up) => { class WithNoPLIC extends Config((site, here, up) => { case PLICKey => None }) + +class WithDebugModuleAbstractDataWords(words: Int = 16) extends Config((site, here, up) => { + case DebugModuleKey => up(DebugModuleKey).map(_.copy(nAbstractDataWords=words)) +})