From 083f34ab23f91a910edfbbc70d35e56fe4331448 Mon Sep 17 00:00:00 2001
From: abejgonzalez <abe.j.gonza@gmail.com>
Date: Thu, 5 Nov 2020 15:44:54 -0800
Subject: [PATCH] Revert Chipyard system | Create new VCU118 Chipyard system

---
 fpga/src/main/scala/vcu118/DigitalTop.scala   | 54 +++++++++++++++++--
 .../chipyard/src/main/scala/System.scala      |  1 +
 2 files changed, 50 insertions(+), 5 deletions(-)

diff --git a/fpga/src/main/scala/vcu118/DigitalTop.scala b/fpga/src/main/scala/vcu118/DigitalTop.scala
index 4a176fca..9fe42bc8 100644
--- a/fpga/src/main/scala/vcu118/DigitalTop.scala
+++ b/fpga/src/main/scala/vcu118/DigitalTop.scala
@@ -8,22 +8,66 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.{DontTouch}
 
-import chipyard.{DigitalTop, DigitalTopModule}
+import chipyard.{DigitalTop, DigitalTopModule, ChipyardSubsystem, ChipyardSubsystemModuleImp}
 
 // ------------------------------------
 // VCU118 DigitalTop
 // ------------------------------------
 
-class VCU118DigitalTop(implicit p: Parameters) extends DigitalTop
-  with sifive.blocks.devices.spi.HasPeripherySPI
-  with CanHaveMasterTLMemPort
+class VCU118DigitalTop(implicit p: Parameters) extends VCU118ChipyardSystem
+  with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
+  with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
+  with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
+  with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
+  with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
+  with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
+  with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
+  with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port
+  with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
+  with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
+  with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
+  with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget
+  with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
+  with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
 {
   override lazy val module = new VCU118DigitalTopModule(this)
 }
 
-class VCU118DigitalTopModule[+L <: VCU118DigitalTop](l: L) extends DigitalTopModule(l)
+class VCU118DigitalTopModule[+L <: VCU118DigitalTop](l: L) extends VCU118ChipyardSystemModule(l)
+  with testchipip.CanHaveTraceIOModuleImp
+  with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
+  with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
+  with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
   with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
+  with chipyard.example.CanHavePeripheryGCDModuleImp
+  with freechips.rocketchip.util.DontTouch
+
+// ------------------------------------
+// VCU118 Chipyard System
+// ------------------------------------
+
+class VCU118ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
+  with HasAsyncExtInterrupts
+  with CanHaveMasterTLMemPort // expose a TL port for outer memory (replaces AXI outer port)
+  with CanHaveMasterAXI4MMIOPort
+  with CanHaveSlaveAXI4Port
+{
+
+  val bootROM  = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
+  val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
+  override lazy val module = new VCU118ChipyardSystemModule(this)
+}
+
+class VCU118ChipyardSystemModule[+L <: VCU118ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer)
+  with HasRTCModuleImp
+  with HasExtInterruptsModuleImp
+  with DontTouch
+
+// ------------------------------------
+// VCU118 Mem Port Mixin
+// ------------------------------------
 
 /** Adds a TileLink port to the system intended to master an MMIO device bus */
 trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala
index f8906e04..bd20ddc7 100644
--- a/generators/chipyard/src/main/scala/System.scala
+++ b/generators/chipyard/src/main/scala/System.scala
@@ -23,6 +23,7 @@ import freechips.rocketchip.util.{DontTouch}
  */
 class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
   with HasAsyncExtInterrupts
+  with CanHaveMasterAXI4MemPort
   with CanHaveMasterAXI4MMIOPort
   with CanHaveSlaveAXI4Port
 {