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model and top reference common modules, need to filter them out from sim to avoid module collisions

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Harrison Liew
2023-03-08 16:11:01 -08:00
parent 54c55875e1
commit 0883993000
1 changed files with 1 additions and 1 deletions
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vlsi/sim.mk
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@@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files)
echo " top_module: $(VLSI_TOP)" >> $@ echo " top_module: $(VLSI_TOP)" >> $@
echo " tb_name: ''" >> $@ # don't specify -top echo " tb_name: ''" >> $@ # don't specify -top
echo " input_files:" >> $@ echo " input_files:" >> $@
for x in $$(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \ for x in $$(comm -23 <(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) <(sort $(VLSI_RTL))) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
echo " input_files_meta: 'append'" >> $@ echo " input_files_meta: 'append'" >> $@