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Update docs to reflect in-tree barstools

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This commit is contained in:
Jerry Zhao
2024-04-19 11:38:00 -07:00
parent 9436aea1e8
commit 088460f266
8 changed files with 15 additions and 32 deletions
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6
docs/Customization/Firrtl-Transforms.rst
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@@ -22,18 +22,18 @@ Where to add transforms
In Chipyard, the FIRRTL compiler is called multiple times to create a "Top" file that contains the DUT and a "Model" file containing the test harness, which instantiates the DUT.
The "Model" file does not contain the DUT's module definition or any of its submodules.
This is done by the ``tapeout`` SBT project (located in ``tools/barstools/tapeout``) which calls ``GenerateModelStageMain`` (a function that wraps the multiple FIRRTL compiler calls and extra transforms).
This is done by the ``tapeout`` SBT project (located in ``tools/tapeout``) which calls ``GenerateModelStageMain`` (a function that wraps the multiple FIRRTL compiler calls and extra transforms).
.. literalinclude:: ../../common.mk
:language: make
:start-after: DOC include start: FirrtlCompiler
:end-before: DOC include end: FirrtlCompiler
If you look inside of the `tools/barstools/tapeout/src/main/scala/transforms/GenerateModelStageMain.scala <https://github.com/ucb-bar/barstools/blob/master/tapeout/src/main/scala/transforms/GenerateModelStageMain.scala>`__ file,
If you look inside of the ``tools/tapeout/src/main/scala/transforms/GenerateModelStageMain.scala`` file,
you can see that FIRRTL is invoked for "Model". Currently, the FIRRTL compiler is agnostic to the ``TOP`` and ``MODEL`` differentiation,
and the user is responsible for providing annotations that will inform the compiler where(``TOP`` vs ``MODEL``) to perform the custom FIRRTL transformations.
For more information on Barstools, please visit the :ref:`Tools/Barstools:Barstools` section.
For more information on the Tapeout sub-project, please visit the :ref:`Tools/Tapeout-Tools:Tapeout-Tools` section.
Examples of transforms
----------------------

13
docs/Customization/Incorporating-Verilog-Blocks.rst
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@@ -33,19 +33,6 @@ different directory from Chisel (Scala) sources.
vsrc/
YourFile.v
In addition to the steps outlined in the previous section on adding a
project to the ``build.sbt`` at the top level, it is also necessary to
add any projects that contain Verilog IP as dependencies to the
``tapeout`` project. This ensures that the Verilog sources are visible
to the downstream FIRRTL passes that provide utilities for integrating
Verilog files into the build process, which are part of the
``tapeout`` package in ``barstools/tapeout``.
.. code-block:: scala
lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
.dependsOn(chisel_testers, example, yourproject)
.settings(commonSettings)
For this concrete GCD example, we will be using a ``GCDMMIOBlackBox``
Verilog module that is defined in the ``chipyard`` project. The Scala