From 0a64a7a503ad9ff70cca557c447ef92036a67b35 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Fri, 26 Jan 2024 16:54:21 -0800
Subject: [PATCH] Expose core cease to top-level IO and connect to harness

This is to use cease as the finish signal for TestDriver, as we don't
have TSI mechanism to signal that the cores have finished running a
binary.
---
 generators/chipyard/src/main/scala/Subsystem.scala     |  9 +++++++++
 .../src/main/scala/config/RadianceConfigs.scala        |  2 ++
 .../src/main/scala/harness/HarnessBinders.scala        |  6 ++++++
 .../chipyard/src/main/scala/iobinders/IOBinders.scala  | 10 +++++++++-
 4 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
index 993dad02..f66d06a9 100644
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -70,10 +70,19 @@ trait CanHaveChosenInDTS { this: BaseSubsystem =>
   }
 }
 
+trait HasCeaseSuccessIO { this: HasTileNotificationSinks =>
+  val success = InModuleBody {
+    val success = IO(Output(Bool()))
+    success := tileCeaseSinkNode.in.head._1.asUInt.andR
+    success
+  }
+}
+
 class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
     with InstantiatesHierarchicalElements
     with HasTileNotificationSinks
     with HasTileInputConstants
+    with HasCeaseSuccessIO
     with CanHavePeripheryCLINT
     with CanHavePeripheryPLIC
     with HasPeripheryDebug
diff --git a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala
index 634f51d4..178f5f03 100644
--- a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala
@@ -41,6 +41,8 @@ class RadianceBaseConfig extends Config(
   new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
   new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++
   new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
+  new chipyard.harness.WithCeaseSuccess ++
+  new chipyard.iobinders.WithCeasePunchThrough ++
   new AbstractConfig)
 
 class RadianceConfig extends Config(
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index 59d4110d..d05062fd 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -282,6 +282,12 @@ class WithSimTSIToUARTTSI extends HarnessBinder({
   }
 })
 
+class WithCeaseSuccess extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: SuccessPort, chipId: Int) => {
+    when (port.io) { th.success := true.B }
+  }
+})
+
 class WithTraceGenSuccess extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: SuccessPort, chipId: Int) => {
     when (port.io) { th.success := true.B }
diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
index 64b1296e..fd02084d 100644
--- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -33,7 +33,7 @@ import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDevi
 import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig}
 import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
-import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule}
+import chipyard.{CanHaveMasterTLMemPort, HasCeaseSuccessIO, ChipyardSystem, ChipyardSystemModule}
 
 import scala.reflect.{ClassTag}
 
@@ -458,6 +458,14 @@ class WithNICIOPunchthrough extends OverrideIOBinder({
   }
 })
 
+class WithCeasePunchThrough extends OverrideIOBinder({
+  (system: HasCeaseSuccessIO) => {
+    val success: Bool = IO(Output(Bool())).suggestName("success")
+    success := system.success.getWrappedValue
+    (Seq(SuccessPort(() => success)), Nil)
+  }
+})
+
 class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({
   (system: TraceGenSystemModuleImp) => {
     val success: Bool = IO(Output(Bool())).suggestName("success")