From 0adfb8b9a7ac75cf284ff4155c763ecc3ac8f950 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 22 Apr 2024 19:46:53 -0700
Subject: [PATCH] Remove FixedPoint fallback to SFC (Fixed types aren't
 generated anymore)

---
 common.mk                                | 9 ++++-----
 docs/Customization/Firrtl-Transforms.rst | 2 +-
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/common.mk b/common.mk
index ea5811ac..beb3c173 100644
--- a/common.mk
+++ b/common.mk
@@ -198,19 +198,18 @@ MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVa
 # DOC include start: FirrtlCompiler
 # There are two possible cases for this step. In the first case, SFC
 # compiles Chisel to CHIRRTL, and MFC compiles CHIRRTL to Verilog. Otherwise,
-# when custom FIRRTL transforms are included or if a Fixed type is used within
-# the dut, SFC compiles Chisel to LowFIRRTL and MFC compiles it to Verilog.
+# when custom FIRRTL transforms are included
+# SFC compiles Chisel to LowFIRRTL and MFC compiles it to Verilog.
 # Users can indicate to the Makefile of custom FIRRTL transforms by setting the
 # "ENABLE_CUSTOM_FIRRTL_PASS" variable.
 #
-# hack: lower to low firrtl if Fixed types are found
 # hack: when using dontTouch, io.cpu annotations are not removed by SFC,
 # hence we remove them manually by using jq before passing them to firtool
 
 $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) &: $(FIRRTL_FILE)
 ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
-	echo $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none) > $(SFC_LEVEL)
-	echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), "$(SFC_REPL_SEQ_MEM)",) > $(EXTRA_FIRRTL_OPTIONS)
+	echo none > $(SFC_LEVEL)
+	echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" > $(EXTRA_FIRRTL_OPTIONS)
 else
 	echo low > $(SFC_LEVEL)
 	echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" "$(SFC_REPL_SEQ_MEM)" > $(EXTRA_FIRRTL_OPTIONS)
diff --git a/docs/Customization/Firrtl-Transforms.rst b/docs/Customization/Firrtl-Transforms.rst
index 7de7aadb..2c552e75 100644
--- a/docs/Customization/Firrtl-Transforms.rst
+++ b/docs/Customization/Firrtl-Transforms.rst
@@ -12,7 +12,7 @@ The Scala FIRRTL Compiler and the MLIR FIRRTL Compiler
 ------------------------------------------------------
 In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler (SFC) and the MLIR FIRRTL compiler (MFC).
 They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster (the generated Verilog will be different). In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will
-compile CHIRRTL into Verilog (as of now, we are using SFC as a backup for cases when MFC doesn't work, e.g., when the design is using Fixed types). By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value,
+compile CHIRRTL into Verilog. By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value,
 we can make the SFC compile Chisel into LowFIRRTL so that our custom FIRRTL passes are applied.
 
 For more information on MLIR FIRRTL Compiler, please visit https://mlir.llvm.org/ and https://circt.llvm.org/.