From 61d1798888438c901fe95328f0b1df3494d7e69c Mon Sep 17 00:00:00 2001
From: Paul Rigge <rigge@berkeley.edu>
Date: Thu, 7 Mar 2019 14:44:16 -0800
Subject: [PATCH] Fix AXI4 example.

I accidentally stumbled into a working AXI4 configuration by multiplying
pbus.beatBytes by 8, but it was fragile. This is the "right way" to add
an AXI4 peripheral.
---
 src/main/scala/example/PWM.scala | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/example/PWM.scala b/src/main/scala/example/PWM.scala
index 04ed4203..2cec926e 100644
--- a/src/main/scala/example/PWM.scala
+++ b/src/main/scala/example/PWM.scala
@@ -105,9 +105,15 @@ trait HasPeripheryPWMAXI4 { this: BaseSubsystem =>
   private val portName = "pwm"
 
   val pwm = LazyModule(new PWMAXI4(
-    PWMParams(address, 8 * pbus.beatBytes))(p))
+    PWMParams(address, pbus.beatBytes))(p))
 
-  pbus.toFixedWidthSlave(Some(portName)) { pwm.node := TLToAXI4() }
+  pbus.toSlave(Some(portName)) {
+    pwm.node :=
+      AXI4Buffer () :=
+      TLToAXI4() :=
+      // toVariableWidthSlave doesn't use holdFirstDeny, which TLToAXI4() needs
+      TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true)
+  }
 }
 
 trait HasPeripheryPWMAXI4ModuleImp extends LazyModuleImp {