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Make instance numbers generic for depth and width

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This commit is contained in:
Edward Wang
2017-07-27 10:12:24 -07:00
committed by edwardcwang
parent 4fc829a570
commit 0bfc7a94df
2 changed files with 8 additions and 7 deletions
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5
macros/src/test/scala/MacroCompilerSpec.scala
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@@ -207,9 +207,10 @@ trait HasSimpleTestGenerator {
writeToLib(lib, Seq(generateSRAM(lib_name, "lib", libWidth, libDepth, libMaskGran, extraPorts))) writeToLib(lib, Seq(generateSRAM(lib_name, "lib", libWidth, libDepth, libMaskGran, extraPorts)))
writeToMem(mem, Seq(generateSRAM(mem_name, "outer", memWidth, memDepth, memMaskGran))) writeToMem(mem, Seq(generateSRAM(mem_name, "outer", memWidth, memDepth, memMaskGran)))
// Number of lib instances needed to hold the mem. // Number of lib instances needed to hold the mem, in both directions.
// Round up (e.g. 1.5 instances = effectively 2 instances) // Round up (e.g. 1.5 instances = effectively 2 instances)
val expectedInstances = math.ceil(memDepth.toFloat / libDepth).toInt val depthInstances = math.ceil(memDepth.toFloat / libDepth).toInt
val widthInstances = math.ceil(memWidth.toFloat / libWidth).toInt
val selectBits = mem_addr_width - lib_addr_width val selectBits = mem_addr_width - lib_addr_width
// Generate the header (contains the circuit statement and the target memory // Generate the header (contains the circuit statement and the target memory

10
macros/src/test/scala/SimpleSplitDepth.scala
View File

@@ -24,7 +24,7 @@ trait HasSimpleDepthTestGenerator extends HasSimpleTestGenerator {
""" """
} }
for (i <- 0 to expectedInstances - 1) { for (i <- 0 to depthInstances - 1) {
// We only support simple masks for now (either libMask == memMask or libMask == 1) // We only support simple masks for now (either libMask == memMask or libMask == 1)
val maskStatement = if (libHasMask) { val maskStatement = if (libHasMask) {
if (libMaskGran.get == memMaskGran.get) { if (libMaskGran.get == memMaskGran.get) {
@@ -58,18 +58,18 @@ trait HasSimpleDepthTestGenerator extends HasSimpleTestGenerator {
node outer_dout_${i} = outer_dout_${i}_0 node outer_dout_${i} = outer_dout_${i}_0
""" """
} }
def generate_outer_dout_tree(i:Int, expectedInstances: Int): String = { def generate_outer_dout_tree(i:Int, depthInstances: Int): String = {
if (i > expectedInstances - 1) { if (i > depthInstances - 1) {
"UInt<1>(\"h0\")" "UInt<1>(\"h0\")"
} else { } else {
"mux(eq(outer_addr_sel, UInt<%d>(\"h%s\")), outer_dout_%d, %s)".format( "mux(eq(outer_addr_sel, UInt<%d>(\"h%s\")), outer_dout_%d, %s)".format(
selectBits, i.toHexString, i, generate_outer_dout_tree(i + 1, expectedInstances) selectBits, i.toHexString, i, generate_outer_dout_tree(i + 1, depthInstances)
) )
} }
} }
output += " outer_dout <= " output += " outer_dout <= "
if (selectBits > 0) { if (selectBits > 0) {
output += generate_outer_dout_tree(0, expectedInstances) output += generate_outer_dout_tree(0, depthInstances)
} else { } else {
output += """mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0"))""" output += """mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0"))"""
} }