From 1bb86cfffe36a31422efcfe2e7946cf151d5c30f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 17 Jul 2019 09:49:12 -0700 Subject: [PATCH 1/8] updated boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 84879571..51bfc070 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 848795715f721b6a88887283179176474a1496b8 +Subproject commit 51bfc070e8b4750f5401b5db235233421ab8deba From 89b312a8891a4df855d82d4accdfb0db20613d65 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 24 Jul 2019 22:42:21 -0700 Subject: [PATCH 2/8] move boom integration to chipyard --- generators/boom | 2 +- .../example/src/main/scala/BoomConfigs.scala | 97 +++++++++++++++++++ .../example/src/main/scala/ConfigMixins.scala | 9 ++ .../example/src/main/scala/Configs.scala | 30 +++--- .../example/src/main/scala/TestHarness.scala | 48 ++++++++- generators/example/src/main/scala/Top.scala | 13 ++- variables.mk | 2 +- 7 files changed, 179 insertions(+), 22 deletions(-) create mode 100644 generators/example/src/main/scala/BoomConfigs.scala diff --git a/generators/boom b/generators/boom index 51bfc070..962e9467 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 51bfc070e8b4750f5401b5db235233421ab8deba +Subproject commit 962e94674ebd859d4798efe44cb6e404be9a5076 diff --git a/generators/example/src/main/scala/BoomConfigs.scala b/generators/example/src/main/scala/BoomConfigs.scala new file mode 100644 index 00000000..e8044080 --- /dev/null +++ b/generators/example/src/main/scala/BoomConfigs.scala @@ -0,0 +1,97 @@ +//****************************************************************************** +// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). +// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. +//------------------------------------------------------------------------------ +// Author: Christopher Celio, Abraham Gonzalez, Ben Korpan, Jerry Zhao +//------------------------------------------------------------------------------ + +package example + +import chisel3._ + +import freechips.rocketchip.config.{Config} +import freechips.rocketchip.subsystem.{WithJtagDTM} + +import boom.common._ + +// --------------------- +// BOOM Configs +// --------------------- + +class SmallBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.SmallBoomConfig) + +class MediumBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.MediumBoomConfig) + +class LargeBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.LargeBoomConfig) + +class MegaBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.MegaBoomConfig) + +class jtagSmallBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.SmallBoomConfig) + +class jtagMediumBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.MediumBoomConfig) + +class jtagLargeBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.LargeBoomConfig) + +class jtagMegaBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.MegaBoomConfig) + +class SmallDualBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.SmallDualBoomConfig) + +class TracedSmallBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.TracedSmallBoomConfig) + +class SmallRV32UnifiedBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.SmallRV32UnifiedBoomConfig) + +// -------------------------- +// BOOM + Rocket Configs +// -------------------------- + +class SmallBoomAndRocketConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.SmallBoomAndRocketConfig) + +class MediumBoomAndRocketConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.MediumBoomAndRocketConfig) + +class DualMediumBoomAndDualRocketConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.DualMediumBoomAndDualRocketConfig) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 895fa86a..17fac94d 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -58,6 +58,15 @@ class WithNormalBoomRocketTop extends Config((site, here, up) => { } }) +/** + * Class to specify a top level BOOM and/or Rocket system with DTM + */ +class WithDTMBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomRocketTopWithDTM()(p)).module) + } +}) + /** * Class to specify a top level BOOM and/or Rocket system with PWM */ diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index c6cfa7a5..c7e70dd2 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -77,11 +77,11 @@ class HwachaL2Config extends Config( class BaseBoomConfig extends Config( new WithBootROM ++ - new boom.system.LargeBoomConfig) + new boom.common.LargeBoomConfig) class SmallBaseBoomConfig extends Config( new WithBootROM ++ - new boom.system.SmallBoomConfig) + new boom.common.SmallBoomConfig) class DefaultBoomConfig extends Config( new WithNormalBoomRocketTop ++ @@ -132,7 +132,7 @@ class DualCoreBoomConfig extends Config( new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig) @@ -142,14 +142,14 @@ class DualCoreSmallBoomConfig extends Config( new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig) class RV32UnifiedBoomConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ - new boom.system.SmallRV32UnifiedBoomConfig) + new boom.common.SmallRV32UnifiedBoomConfig) class BoomL2Config extends Config( new WithInclusiveCache ++ @@ -161,22 +161,22 @@ class BoomL2Config extends Config( class BaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new boom.system.WithRenumberHarts ++ + new boom.common.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(1) ++ + new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) class SmallBaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new boom.system.WithRenumberHarts ++ + new boom.common.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(1) ++ + new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) @@ -223,11 +223,11 @@ class GPIOBoomAndRocketConfig extends Config( class DualCoreBoomAndOneRocketConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ - new boom.system.WithRenumberHarts ++ + new boom.common.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) @@ -237,12 +237,12 @@ class DualBoomAndOneHwachaRocketConfig extends Config( new WithBootROM ++ new WithMultiRoCC ++ new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket - new boom.system.WithRenumberHarts(rocketFirst = true) ++ + new boom.common.WithRenumberHarts(rocketFirst = true) ++ new hwacha.DefaultHwachaConfig ++ new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) @@ -250,12 +250,12 @@ class DualBoomAndOneHwachaRocketConfig extends Config( class RV32BoomAndRocketConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ - new boom.system.WithRenumberHarts ++ + new boom.common.WithRenumberHarts ++ new boom.common.WithBoomRV32 ++ new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(1) ++ + new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithRV32 ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index c59a081e..778fcc81 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -8,14 +8,19 @@ import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp +import freechips.rocketchip.devices.debug.{Debug} -// -------------------------- +// ------------------------------- // BOOM and/or Rocket Test Harness -// -------------------------- +// ------------------------------- case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]] +case object BuildBoomRocketTopWithDTM extends Field[(Clock, Bool, Parameters) => BoomRocketTopWithDTMModule[BoomRocketTopWithDTM]] -class BoomRocketTestHarness(implicit val p: Parameters) extends Module { +/** + * Test harness using TSI to bringup the system + */ +class TestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val success = Output(Bool()) }) @@ -24,6 +29,7 @@ class BoomRocketTestHarness(implicit val p: Parameters) extends Module { override def desiredName = "TestHarness" val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p) + dut.debug := DontCare dut.connectSimAXIMem() dut.connectSimAXIMMIO() @@ -41,5 +47,41 @@ class BoomRocketTestHarness(implicit val p: Parameters) extends Module { axi.w.bits := DontCare } }) + io.success := dut.connectSimSerial() } + +/** + * Test harness using the Debug Test Module (DTM) to bringup the system + */ +class TestHarnessWithDTM(implicit p: Parameters) extends Module +{ + val io = IO(new Bundle { + val success = Output(Bool()) + }) + + // force Chisel to rename module + override def desiredName = "TestHarness" + + val dut = p(BuildBoomRocketTopWithDTM)(clock, reset.toBool, p) + + dut.reset := reset.asBool | dut.debug.ndreset + dut.connectSimAXIMem() + dut.connectSimAXIMMIO() + dut.dontTouchPorts() + dut.tieOffInterrupts() + dut.l2_frontend_bus_axi4.foreach(axi => { + axi.tieoff() + experimental.DataMirror.directionOf(axi.ar.ready) match { + case core.ActualDirection.Input => + axi.r.bits := DontCare + axi.b.bits := DontCare + case core.ActualDirection.Output => + axi.aw.bits := DontCare + axi.ar.bits := DontCare + axi.w.bits := DontCare + } + }) + + Debug.connectDebug(dut.debug, clock, reset.asBool, io.success) +} diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index a3fa99f8..b861fdec 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -12,9 +12,9 @@ import testchipip._ import sifive.blocks.devices.gpio._ -// ------------------------------- +// ------------------------------------ // BOOM and/or Rocket Top Level Systems -// ------------------------------- +// ------------------------------------ class BoomRocketTop(implicit p: Parameters) extends boom.system.BoomRocketSystem with HasNoDebug @@ -67,3 +67,12 @@ class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO) extends BoomRocketTopModule(l) with HasPeripheryGPIOModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomRocketTopWithDTM(implicit p: Parameters) extends boom.system.BoomRocketSystem +{ + override lazy val module = new BoomRocketTopWithDTMModule(this) +} + +class BoomRocketTopWithDTMModule[+L <: BoomRocketTopWithDTM](l: L) extends boom.system.BoomRocketSystemModule(l) diff --git a/variables.mk b/variables.mk index a0c6a9af..fa7bb494 100644 --- a/variables.mk +++ b/variables.mk @@ -29,7 +29,7 @@ SUB_PROJECT ?= example ifeq ($(SUB_PROJECT),example) SBT_PROJECT ?= example - MODEL ?= BoomRocketTestHarness + MODEL ?= TestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) CONFIG ?= DefaultRocketConfig From a8dbc391a15334050aa4b4f658343d8c192565f0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 24 Jul 2019 22:55:00 -0700 Subject: [PATCH 3/8] remove boom variables | update ci --- .circleci/defaults.sh | 2 +- generators/boom | 2 +- variables.mk | 12 ------------ 3 files changed, 2 insertions(+), 14 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 25b365d8..cdccc3ba 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -38,7 +38,7 @@ declare -A mapping mapping["example"]="SUB_PROJECT=example" mapping["boomexample"]="SUB_PROJECT=example CONFIG=DefaultBoomConfig" mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig" -mapping["boom"]="SUB_PROJECT=boom" +mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig" mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=BlockDeviceModelRocketConfig TOP=BoomRocketTopWithBlockDevice" mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaL2Config GENERATOR_PACKAGE=hwacha" diff --git a/generators/boom b/generators/boom index 962e9467..3a06403d 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 962e94674ebd859d4798efe44cb6e404be9a5076 +Subproject commit 3a06403df71d46f2c42f9baac134a3b2997595e5 diff --git a/variables.mk b/variables.mk index fa7bb494..66eb0518 100644 --- a/variables.mk +++ b/variables.mk @@ -38,18 +38,6 @@ ifeq ($(SUB_PROJECT),example) TB ?= TestDriver TOP ?= BoomRocketTop endif -# for BOOM developers -ifeq ($(SUB_PROJECT),boom) - SBT_PROJECT ?= boom - MODEL ?= TestHarness - VLOG_MODEL ?= TestHarness - MODEL_PACKAGE ?= boom.system - CONFIG ?= LargeBoomConfig - CONFIG_PACKAGE ?= boom.system - GENERATOR_PACKAGE ?= boom.system - TB ?= TestDriver - TOP ?= BoomRocketSystem -endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) SBT_PROJECT ?= rocketchip From 6d8a6b2412fb3f45fef470b401275b721658c3c7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 1 Aug 2019 11:22:05 -0700 Subject: [PATCH 4/8] remove header from BoomConfigs.scala --- generators/example/src/main/scala/BoomConfigs.scala | 7 ------- 1 file changed, 7 deletions(-) diff --git a/generators/example/src/main/scala/BoomConfigs.scala b/generators/example/src/main/scala/BoomConfigs.scala index e8044080..f328b902 100644 --- a/generators/example/src/main/scala/BoomConfigs.scala +++ b/generators/example/src/main/scala/BoomConfigs.scala @@ -1,10 +1,3 @@ -//****************************************************************************** -// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). -// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. -//------------------------------------------------------------------------------ -// Author: Christopher Celio, Abraham Gonzalez, Ben Korpan, Jerry Zhao -//------------------------------------------------------------------------------ - package example import chisel3._ From cd48271b5314d0605bea01223a3f97b091ef63b8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 1 Aug 2019 22:33:21 -0700 Subject: [PATCH 5/8] Added DTM docs | bumped BOOM --- docs/Advanced-Usage/DTM-Debugging.rst | 48 +++++++++++++++++++++++++++ docs/Advanced-Usage/index.rst | 1 + generators/boom | 2 +- 3 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 docs/Advanced-Usage/DTM-Debugging.rst diff --git a/docs/Advanced-Usage/DTM-Debugging.rst b/docs/Advanced-Usage/DTM-Debugging.rst new file mode 100644 index 00000000..953e9cbd --- /dev/null +++ b/docs/Advanced-Usage/DTM-Debugging.rst @@ -0,0 +1,48 @@ +Debugging with DTM/JTAG +=============================== + +By default, Chipyard is not setup to use the Debug Test Module (DTM) to bringup the core. +Instead, Chipyard uses TSI commands to bringup the core (which normally results in a faster simulation). +However, if you want to use JTAG, you must do the following steps to setup a DTM enabled system. + +Creating a DTM/JTAG Config +------------------------------------------- + +First, a DTM config must be created for the system that you want to create. +This involves specifying the SoC top-level to add a DTM as well as configuring that DTM to use JTAG. + +.. code-block:: scala + + class DTMBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.SmallBoomConfig) + +In this example, the ``WithDTMBoomRocketTop`` mixin specifies that the top-level SoC will instantiate a DTM. +The ``WithJtagDTM`` will configure that instantiated DTM to use JTAG as the bringup method (note: this can be removed if you want a DTM-only bringup). +The rest of the mixins specify the rest of the system (cores, accelerators, etc). + +Starting the DTM Simulation +------------------------------------------- + +After creating the config, call the ``make`` command like the following: + +.. code-block:: bash + + cd sims/verilator + # or + cd sims/vcs + + make CONFIG=DTMBoomConfig TOP=BoomRocketTopWithDTM MODEL=TestHarnessWithDTM + +In this example, this will use the config that you previously specified, as well as set the other parameters that are needed to satisfy the build system. +After that point, you should have a JTAG enabled simulation that you can attach to using OpenOCD and GDB! + +Debugging with JTAG +------------------------------------------------------- + +Please refer to the following resources on how to debug with JTAG. + +* https://github.com/chipsalliance/rocket-chip#-debugging-with-gdb +* https://github.com/riscv/riscv-isa-sim#debugging-with-gdb diff --git a/docs/Advanced-Usage/index.rst b/docs/Advanced-Usage/index.rst index 62dd11aa..1f313e60 100644 --- a/docs/Advanced-Usage/index.rst +++ b/docs/Advanced-Usage/index.rst @@ -9,3 +9,4 @@ They expect you to know about Chisel, Parameters, Configs, etc. :caption: Getting Started: Heterogeneous-SoCs + DTM-Debugging diff --git a/generators/boom b/generators/boom index 3a06403d..609cf36e 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 3a06403df71d46f2c42f9baac134a3b2997595e5 +Subproject commit 609cf36eea7da73aad9f7abf379320615ae7e554 From 3baad45dce3e4fc90b623bc035ace567725d751c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 2 Aug 2019 21:43:23 -0700 Subject: [PATCH 6/8] update boom to master --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 609cf36e..96616414 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 609cf36eea7da73aad9f7abf379320615ae7e554 +Subproject commit 96616414e17474c4196ddea00ce9ea41d52dc143 From 717c4658ffa22717431db543bf5fc40770aca5cf Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 6 Aug 2019 10:44:31 -0700 Subject: [PATCH 7/8] update boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 96616414..4e9d496d 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 96616414e17474c4196ddea00ce9ea41d52dc143 +Subproject commit 4e9d496d3678cc5ae005669a448ae9e89f8ae847 From 34f76056effe17f939caf52a92a6b334899f09aa Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 6 Aug 2019 22:57:49 -0600 Subject: [PATCH 8/8] Update docs/Advanced-Usage/DTM-Debugging.rst Co-Authored-By: Jerry Zhao --- docs/Advanced-Usage/DTM-Debugging.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/Advanced-Usage/DTM-Debugging.rst b/docs/Advanced-Usage/DTM-Debugging.rst index 953e9cbd..bf033fec 100644 --- a/docs/Advanced-Usage/DTM-Debugging.rst +++ b/docs/Advanced-Usage/DTM-Debugging.rst @@ -3,6 +3,8 @@ Debugging with DTM/JTAG By default, Chipyard is not setup to use the Debug Test Module (DTM) to bringup the core. Instead, Chipyard uses TSI commands to bringup the core (which normally results in a faster simulation). +TSI simulations use the SimSerial interface to directly write the test binary into memory, while the DTM +executes a small loop of code to write the test binary byte-wise into memory. However, if you want to use JTAG, you must do the following steps to setup a DTM enabled system. Creating a DTM/JTAG Config