From 0d6e971d17a01b4bd6db0780004a0e5f5b4a9e30 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 18 Mar 2021 20:02:15 -0700 Subject: [PATCH] Update docs/Advanced-Concepts/Chip-Communication.rst Co-authored-by: alonamid --- docs/Advanced-Concepts/Chip-Communication.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index 5c18783d..f9fa8229 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -210,7 +210,7 @@ Bringup Setup of the Example Test Chip after Tapeout ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Assuming this example test chip is taped out and now ready to be tested, we can communicate with the chip using this serial-link. -For example, some Berkeley tapeouts of Chipyard chips have an FPGA running a RISC-V soft-core that is able to speak to the DUT. +For example, a common test setup used at Berkeley to evaluate Chipyard-based test-chips includes an FPGA running a RISC-V soft-core that is able to speak to the DUT (over an FMC). This RISC-V soft-core would serve as the host of the test that will run on the DUT. This is done by the RISC-V soft-core running FESVR, sending TSI commands to a ``SerialAdapter`` / ``TLSerdesser`` programmed on the FPGA. Once the commands are converted to serialized TileLink, then they can be sent over some medium to the DUT