diff --git a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
index 3a035a10..4027cbcf 100644
--- a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
+++ b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
@@ -14,30 +14,26 @@ import chipyard._
 import chipyard.harness._
 
 import testchipip._
+import chipyard.iobinders._
 
-class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarnessBinder({
-  (system: CanHavePeripheryUARTTSI, th: HasHarnessInstantiators, ports: Seq[UARTTSIIO]) => {
-    implicit val p = chipyard.iobinders.GetSystemParameters(system)
-    require(ports.size <= 1)
+class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
     val nexysvideoth = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
-    ports.map({ port =>
-      nexysvideoth.io_uart_bb.bundle <> port.uart
-      nexysvideoth.other_leds(1) := port.dropped
-      nexysvideoth.other_leds(2) := port.tsi2tl_state(0)
-      nexysvideoth.other_leds(3) := port.tsi2tl_state(1)
-      nexysvideoth.other_leds(4) := port.tsi2tl_state(2)
-      nexysvideoth.other_leds(5) := port.tsi2tl_state(3)
-    })
+    nexysvideoth.io_uart_bb.bundle <> port.io.uart
+    nexysvideoth.other_leds(1) := port.io.dropped
+    nexysvideoth.other_leds(2) := port.io.tsi2tl_state(0)
+    nexysvideoth.other_leds(3) := port.io.tsi2tl_state(1)
+    nexysvideoth.other_leds(4) := port.io.tsi2tl_state(2)
+    nexysvideoth.other_leds(5) := port.io.tsi2tl_state(3)
   }
 })
 
-class WithNexysVideoDDRTL extends OverrideHarnessBinder({
-  (system: CanHaveMasterTLMemPort, th: HasHarnessInstantiators, ports: Seq[HeterogeneousBag[TLBundle]]) => {
-    require(ports.size == 1)
+class WithNexysVideoDDRTL extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: TLMemPort) => {
     val nexysTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
     val bundles = nexysTh.ddrClient.get.out.map(_._1)
     val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
     bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
-    ddrClientBundle <> ports.head
+    ddrClientBundle <> port.io
   }
 })