From 0f34247378185ff1dd83b5c731df4e1b3c76075a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 15:51:25 -0700 Subject: [PATCH] add section on where to find verilog --- docs/Getting-Started/Running-A-Simulation.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Getting-Started/Running-A-Simulation.rst index e67b3813..899d1d41 100644 --- a/docs/Getting-Started/Running-A-Simulation.rst +++ b/docs/Getting-Started/Running-A-Simulation.rst @@ -88,6 +88,9 @@ For example: Note: You need to specify all the make variables once again to match what the build gave to run the assembly tests or the benchmarks or the binaries if you are using the make option. +Finally, in the ``generated-src/<...>--/`` directory resides all of the collateral and Verilog source files for the build/simulation. +Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``. + FPGA Accelerated Simulation --------------------------- FireSim enables simulations at 1000x-100000x the speed of standard software simulation.