Fix typos
This commit is contained in:
@@ -156,7 +156,12 @@ Loadmem files should be ELF files. In the most common use case, this can be the
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.. code-block:: shell
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make run-binary BINARY=test.riscv LOADMEM=test.riscv
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make run-binary BINART=test.riscv LOADMEM=1
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Usually the ``LOADMEM`` ELF is the same as the ``BINARY`` ELF, so ``LOADMEM=1`` can be used as a shortcut.
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.. code-block:: shell
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make run-binary BINARY=test.riscv LOADMEM=1
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Generating Waveforms
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-----------------------
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@@ -185,7 +185,7 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBind
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(system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {
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val p: Parameters = chipyard.iobinders.GetSystemParameters(system)
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(ports zip system.memAXI4Node.edges.in).map { case (port, edge) =>
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// TODO FIX: This currently makes each SimDRAM contian the entire memory space
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// TODO FIX: This currently makes each SimDRAM contain the entire memory space
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val memSize = p(ExtMem).get.master.size
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val memBase = p(ExtMem).get.master.base
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val lineSize = p(CacheBlockBytes)
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@@ -7,18 +7,18 @@ usage() {
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echo ""
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echo "Options"
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echo " --help -h : Display this message"
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echo " -n <n> : Mumber of harts"
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echo " -n <n> : Number of harts"
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echo " -b <elf> : Binary to run in spike"
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echo " -p <pc> : PC to take checkpoint at [default 0x80000000]"
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echo " -c <cycles>: Cycles after PC to take checkpoint at [default 0]"
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echo " -m <isa> : ISA to pass to spike for checkpoint generation [defualt rv64gc]"
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echo " -i <insns> : Instructions after PC to take checkpoint at [default 0]"
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echo " -m <isa> : ISA to pass to spike for checkpoint generation [default rv64gc]"
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exit "$1"
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}
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NHARTS=1
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BINARY=""
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PC="0x80000000"
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CYCLES=0
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INSNS=0
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ISA="rv64gc"
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while [ "$1" != "" ];
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do
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@@ -34,9 +34,9 @@ do
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-p )
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shift
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PC=$1 ;;
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-c )
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-i )
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shift
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CYCLES=$1 ;;
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INSNS=$1 ;;
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-m )
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shift
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ISA=$1 ;;
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@@ -50,7 +50,7 @@ BASEMEM="$((0x80000000)):$((0x10000000))"
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SPIKEFLAGS="-p$NHARTS --pmpregions=0 --isa=$ISA -m$BASEMEM"
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BASENAME=$(basename -- $BINARY)
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DIRNAME=$BASENAME.$PC.$CYCLES.loadarch
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DIRNAME=$BASENAME.$PC.$INSNS.loadarch
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echo "Generating loadarch directory $DIRNAME"
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rm -rf $DIRNAME
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mkdir -p $DIRNAME
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@@ -63,7 +63,7 @@ SPIKECMD_FILE=$DIRNAME/spikecmd.sh
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echo "Generating state capture spike interactive commands in $CMDS_FILE"
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echo "until pc 0 $PC" >> $CMDS_FILE
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echo "rs $CYCLES" >> $CMDS_FILE
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echo "rs $INSNS" >> $CMDS_FILE
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echo "dump" >> $CMDS_FILE
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for (( h=0; h<$NHARTS; h++ ))
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do
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@@ -113,8 +113,6 @@ do
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done
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echo "quit" >> $CMDS_FILE
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#cat $CMDS_FILE
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echo "spike -d --debug-cmd=$CMDS_FILE $SPIKEFLAGS $BINARY" > $SPIKECMD_FILE
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echo "Capturing state at checkpoint to spikeout"
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@@ -25,6 +25,8 @@ HELP_PROJECT_VARIABLES = \
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HELP_SIMULATION_VARIABLES = \
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" BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \
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" LOADMEM = riscv elf binary that should be loaded directly into simulated DRAM. LOADMEM=1 will load the BINARY elf" \
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" LOADARCH = path to a architectural checkpoint directory that should end in .loadarch/, for restoring from a checkpoint" \
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" VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" \
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" timeout_cycles = number of clock cycles before simulator times out, defaults to 10000000" \
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" bmark_timeout_cycles = number of clock cycles before benchmark simulator times out, defaults to 100000000"
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