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Merge pull request #1682 from ucb-bar/fpga-minor-fix

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REFACTOR: rename arty35t explicitly
This commit is contained in:
-T.K.-
2023-12-04 08:28:54 -08:00
committed by GitHub
parent 9ae012fe5d 00c4992842
commit 134c76c62f
4 changed files with 10 additions and 10 deletions
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4
.github/scripts/defaults.sh vendored
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@@ -34,7 +34,7 @@ grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipya
grouping["group-constellation"]="chipyard-constellation" grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boom" grouping["group-tracegen"]="tracegen tracegen-boom"
grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar" grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar"
grouping["group-fpga"]="arty arty100t nexysvideo vc707 vcu118" grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"
# key value store to get the build strings # key value store to get the build strings
declare -A mapping declare -A mapping
@@ -79,7 +79,7 @@ mapping["rocketchip-tlsimple"]="SUB_PROJECT=rocketchip CONFIG=TLSimpleUnitTestCo
mapping["rocketchip-tlwidth"]="SUB_PROJECT=rocketchip CONFIG=TLWidthUnitTestConfig" mapping["rocketchip-tlwidth"]="SUB_PROJECT=rocketchip CONFIG=TLWidthUnitTestConfig"
mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig" mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig"
mapping["arty"]="SUB_PROJECT=arty verilog" mapping["arty35t"]="SUB_PROJECT=arty35t verilog"
mapping["arty100t"]="SUB_PROJECT=arty100t verilog" mapping["arty100t"]="SUB_PROJECT=arty100t verilog"
mapping["nexysvideo"]="SUB_PROJECT=nexysvideo verilog" mapping["nexysvideo"]="SUB_PROJECT=nexysvideo verilog"
mapping["vc707"]="SUB_PROJECT=vc707 verilog" mapping["vc707"]="SUB_PROJECT=vc707 verilog"

6
fpga/Makefile
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@@ -72,11 +72,11 @@ ifeq ($(SUB_PROJECT),nexysvideo)
FPGA_BRAND ?= xilinx FPGA_BRAND ?= xilinx
endif endif
ifeq ($(SUB_PROJECT),arty) ifeq ($(SUB_PROJECT),arty35t)
# TODO: Fix with Arty # TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms SBT_PROJECT ?= fpga_platforms
MODEL ?= ArtyFPGATestHarness MODEL ?= Arty35THarness
VLOG_MODEL ?= ArtyFPGATestHarness VLOG_MODEL ?= Arty35THarness
MODEL_PACKAGE ?= chipyard.fpga.arty MODEL_PACKAGE ?= chipyard.fpga.arty
CONFIG ?= TinyRocketArtyConfig CONFIG ?= TinyRocketArtyConfig
CONFIG_PACKAGE ?= chipyard.fpga.arty CONFIG_PACKAGE ?= chipyard.fpga.arty

8
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -15,19 +15,19 @@ import chipyard.harness.{HarnessBinder}
import chipyard.iobinders._ import chipyard.iobinders._
class WithArtyDebugResetHarnessBinder extends HarnessBinder({ class WithArtyDebugResetHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: DebugResetPort) => { case (th: Arty35THarness, port: DebugResetPort) => {
th.dut_ndreset := port.io // Debug module reset th.dut_ndreset := port.io // Debug module reset
} }
}) })
class WithArtyJTAGResetHarnessBinder extends HarnessBinder({ class WithArtyJTAGResetHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: JTAGResetPort) => { case (th: Arty35THarness, port: JTAGResetPort) => {
port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
} }
}) })
class WithArtyJTAGHarnessBinder extends HarnessBinder({ class WithArtyJTAGHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: JTAGPort) => { case (th: Arty35THarness, port: JTAGPort) => {
val jtag_wire = Wire(new JTAGIO) val jtag_wire = Wire(new JTAGIO)
jtag_wire.TDO.data := port.io.TDO jtag_wire.TDO.data := port.io.TDO
jtag_wire.TDO.driven := true.B jtag_wire.TDO.driven := true.B
@@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({
}) })
class WithArtyUARTHarnessBinder extends HarnessBinder({ class WithArtyUARTHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: UARTPort) => { case (th: Arty35THarness, port: UARTPort) => {
withClockAndReset(th.clock_32MHz, th.ck_rst) { withClockAndReset(th.clock_32MHz, th.ck_rst) {
IOBUF(th.uart_rxd_out, port.io.txd) IOBUF(th.uart_rxd_out, port.io.txd)
port.io.rxd := IOBUF(th.uart_txd_in) port.io.rxd := IOBUF(th.uart_txd_in)

2
fpga/src/main/scala/arty/TestHarness.scala
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@@ -10,7 +10,7 @@ import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
import chipyard.harness.{HasHarnessInstantiators} import chipyard.harness.{HasHarnessInstantiators}
class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators { class Arty35THarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
// Convert harness resets from Bool to Reset type. // Convert harness resets from Bool to Reset type.
val hReset = Wire(Reset()) val hReset = Wire(Reset())
hReset := ~ck_rst hReset := ~ck_rst