Reorganize AbstractConfig further
This commit is contained in:
Jerry Zhao
@@ -15,24 +15,24 @@ class AbstractConfig extends Config(
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// Set up TestHarness
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// ================================================
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// The HarnessBinders control generation of hardware in the TestHarness
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new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present
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new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
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new chipyard.harness.WithSimTSIOverSerialTL ++ // add external serial-adapter and RAM
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new chipyard.harness.WithSimJTAGDebug ++ // add SimJTAG if JTAG for debug exposed
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new chipyard.harness.WithSimDMI ++ // add SimJTAG if DMI exposed
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new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present
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new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled
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new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled
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new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present
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new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present
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new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present
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new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port
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new chipyard.harness.WithClockFromHarness ++ // all Clock I/O in ChipTop should be driven by harnessClockInstantiator
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new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness
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new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz
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new chipyard.harness.WithUARTAdapter ++ /** add UART adapter to display UART on stdout, if uart is present */
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new chipyard.harness.WithBlackBoxSimMem ++ /** add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled */
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new chipyard.harness.WithSimTSIOverSerialTL ++ /** add external serial-adapter and RAM */
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new chipyard.harness.WithSimJTAGDebug ++ /** add SimJTAG if JTAG for debug exposed */
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new chipyard.harness.WithSimDMI ++ /** add SimJTAG if DMI exposed */
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new chipyard.harness.WithGPIOTiedOff ++ /** tie-off chiptop GPIOs, if GPIOs are present */
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new chipyard.harness.WithSimSPIFlashModel ++ /** add simulated SPI flash memory, if SPI is enabled */
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new chipyard.harness.WithSimAXIMMIO ++ /** add SimAXIMem for axi4 mmio port, if enabled */
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new chipyard.harness.WithTieOffInterrupts ++ /** tie-off interrupt ports, if present */
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new chipyard.harness.WithTieOffL2FBusAXI ++ /** tie-off external AXI4 master, if present */
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new chipyard.harness.WithCustomBootPinPlusArg ++ /** drive custom-boot pin with a plusarg, if custom-boot-pin is present */
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new chipyard.harness.WithSimUARTToUARTTSI ++ /** connect a SimUART to the UART-TSI port */
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new chipyard.harness.WithClockFromHarness ++ /** all Clock I/O in ChipTop should be driven by harnessClockInstantiator */
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new chipyard.harness.WithResetFromHarness ++ /** reset controlled by harness */
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new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ /** generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz */
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// ================================================
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// Set up I/O harness
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// Set up I/O cells + punch I/Os in ChipTop
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// ================================================
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// The IOBinders instantiate ChipTop IOs to match desired digital IOs
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// IOCells are generated for "Chip-like" IOs
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@@ -61,66 +61,71 @@ class AbstractConfig extends Config(
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// Set up External Memory and IO Devices
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// ================================================
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// External memory section
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new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */
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new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */
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testchipip.serdes.SerialTLParams(
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client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), /** serial-tilelink interface will master the FBUS, and support 4 idBits */
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width = 32 /** serial-tilelink interface with 32 lanes */
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width = 32 /** serial-tilelink interface with 32 lanes */
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)
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)) ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 AXI-4 memory channels */
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */
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new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */
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// MMIO device section
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new chipyard.config.WithUART ++ /** add a UART */
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new chipyard.config.WithUART ++ /** add a UART */
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// ================================================
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// Set up Debugging
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// Set up Debug/Bringup/Testing Features
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// ================================================
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// JTAG
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new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data capacity */
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// new chipyard.config.WithJTAGDTMKey(idcodeVersion = 2, partNum = 0x000, manufId = 0x489, debugIdleCycles = 5) ++
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// new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
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new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data word capacity */
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new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */
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// Boot Select Pins
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new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */
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new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */
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// ================================================
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// Set up Interrupts
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// ================================================
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// CLINT and PLIC related settings goes here
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */
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// ================================================
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// Set up Tiles
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// ================================================
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// core settings goes here
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// tile-local settings goes here
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// ================================================
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// Set up Memory system
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// ================================================
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// On-chip memory section
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new chipyard.config.WithBootROM ++ /** use default bootrom */
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new testchipip.soc.WithMbusScratchpad(base = 0x08000000, /** add 64 KiB on-chip scratchpad */
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new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS (embedded in BootROM) */
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new chipyard.config.WithBootROM ++ /** use default bootrom */
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new testchipip.soc.WithMbusScratchpad(base = 0x08000000, /** add 64 KiB on-chip scratchpad */
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size = 64 * 1024) ++
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// Cache settings
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new chipyard.config.WithL2TLBs(1024) ++ /** use L2 TLBs */
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive L2 cache */
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// Memory Bus settings
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new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 memory channels */
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */
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new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */
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// Coherency settings
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive LLC cache as root of coherence*/
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// Bus/interconnect settings
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */
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// ================================================
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// Set up power, reset and clocking
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// ================================================
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// clocking
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// ChipTop clock IO/PLL/Divider/Mux settings
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new chipyard.clocking.WithPassthroughClockGenerator ++
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// DigitalTop-internal clocking settings
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new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ /** leave the bus clocks undriven by sbus */
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new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */
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new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++
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new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */
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new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", /** create a "uncore" clock group tieing all the bus clocks together */
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Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"),
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Seq("tile"))) ++
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new chipyard.config.WithPeripheryBusFrequency(500.0) ++ /** Default 500 MHz pbus */
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new chipyard.config.WithMemoryBusFrequency(500.0) ++ /** Default 500 MHz mbus */
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@@ -129,10 +134,8 @@ class AbstractConfig extends Config(
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new chipyard.config.WithFrontBusFrequency(500.0) ++ /** Default 500 MHz fbus */
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new chipyard.config.WithOffchipBusFrequency(500.0) ++ /** Default 500 MHz obus */
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new chipyard.config.WithInheritBusFrequencyAssignments ++ /** Unspecified clocks within a bus will receive the bus frequency if set */
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new chipyard.config.WithNoSubsystemDrivenClocks ++ /** drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks */
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new chipyard.clocking.WithPassthroughClockGenerator ++
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// reset
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// power
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@@ -140,6 +143,5 @@ class AbstractConfig extends Config(
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// ==================================
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// Base Settings
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// ==================================
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new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS */
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new freechips.rocketchip.system.BaseConfig /** "base" rocketchip system */
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)
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