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made vlsi flow slightly cleaner

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Nayiri Krzysztofowicz
2023-03-13 13:43:10 -07:00
parent dfc01a2d0f
commit 1811d6fbb1
2 changed files with 3 additions and 9 deletions
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8
.github/workflows/chipyard-full-flow.yml vendored
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@@ -142,10 +142,6 @@ jobs:
echo "drc.magic.magic_bin: $PWD/.conda-signoff/bin/magic" >> tutorial.yml
echo "lvs.netgen.netgen_bin: $PWD/.conda-signoff/bin/netgen" >> tutorial.yml
echo "" >> tutorial.yml
echo "# RocketTile clock name is 'clock'" >> tutorial.yml
echo "vlsi.inputs.clocks: [" >> tutorial.yml
echo " {name: clock, period: 30ns, uncertainty: 3ns}" >> tutorial.yml
echo "]" >> tutorial.yml
echo "# speed up tutorial runs & declutter log output" >> tutorial.yml
echo "par.openroad.timing_driven: false" >> tutorial.yml
echo "par.openroad.write_reports: false" >> tutorial.yml
@@ -154,9 +150,9 @@ jobs:
conda config --remove channels defaults
export tutorial=sky130-openroad
export EXTRA_CONFS="example-designs/sky130-openroad-rockettile.yml tutorial.yml"
export EXTRA_CONFS=tutorial.yml
export VLSI_TOP=RocketTile
make buildfile
make buildfile -B
make syn
# openroad freezes during some write commands after detailed route
# so need to stop the flow & run last step separately