[docs] update documentation [ci skip] (#393)

docs/VLSI/Advanced-Usage.rst

@@ -5,11 +5,11 @@ Advanced Usage
 
 Alternative RTL Flows
 ---------------------
-The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to append the following environment variables to the ``make buildfile`` command (or edit them directly in the Makefile).
+The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom Verilog module through, one only needs to append the following environment variables to the ``make buildfile`` command (or edit them directly in the Makefile).
 
 .. code-block:: shell
 
-    CUSTOM_VLOG=<your verilog files>
+    CUSTOM_VLOG=<your Verilog files>
     VLSI_TOP=<your top module>
 
 ``CUSTOM_VLOG`` breaks the dependency on the rest of the Chipyard infrastructure and does not start any Chisel/FIRRTL elaboration. ``VLSI_TOP`` selects the top module from your custom Verilog files.
@@ -32,7 +32,7 @@ For ``make par``:
 
     ./example-vlsi -e /path/to/env.yml -p /path/to/syn-output-full.json -o /path/to/par-input.json --obj_dir /path/to/build syn-to-par
     ./example-vlsi -e /path/to/env.yml -p /path/to/par-input.json --obj_dir /path/to/build par
-    
+
 A ``syn-to-par`` action translates the synthesis output configuration into an input configuration given by ``-o``. Then, this is passed to the ``par`` action.
 
 For more information about all the options that can be passed to the Hammer command-line driver, please see the Hammer documentation.