diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index c9892aa8..9588d80e 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -56,5 +56,5 @@ class NoCoresArty100TConfig extends Config( class BringupArty100TConfig extends Config( new WithArty100TSerialTLToGPIO ++ new WithArty100TTweaks(freqMHz = 50) ++ - new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++ + new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialParams(freqMHz=50)) ++ new chipyard.ChipBringupHostConfig) diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index d6371ed5..d1af6fdc 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -53,8 +53,8 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({ harnessIO match { case io: DecoupledSerialIO => { val clkIO = io match { - case io: LocallySyncSerialIO => IOPin(io.clock_out) - case io: ExternallySyncSerialIO => IOPin(io.clock_in) + case io: InternalSyncSerialIO => IOPin(io.clock_out) + case io: ExternalSyncSerialIO => IOPin(io.clock_in) } val packagePinsWithPackageIOs = Seq( ("G13", clkIO), @@ -78,10 +78,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({ // Don't add IOB to the clock, if its an input io match { - case io: LocallySyncSerialIO => packagePinsWithPackageIOs foreach { case (pin, io) => { + case io: InternalSyncSerialIO => packagePinsWithPackageIOs foreach { case (pin, io) => { artyTh.xdc.addIOB(io) }} - case io: ExternallySyncSerialIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => { + case io: ExternalSyncSerialIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => { artyTh.xdc.addIOB(io) }} } diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index cef46e04..c234e21a 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -65,8 +65,8 @@ class AbstractConfig extends Config( new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface testchipip.serdes.SerialTLParams( - client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits - width = 32 // serial-tilelink interface with 32 lanes + client = Some(testchipip.serdes.SerialTLClientParams()), // serial-tilelink interface will master the FBUS, and support 4 idBits + phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32) // serial-tilelink interface with 32 lanes ) )) ++ new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index ffcb3f77..583d40bc 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -22,8 +22,18 @@ class ChipLikeRocketConfig extends Config( //================================== // Set up I/O //================================== - new testchipip.serdes.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO - new testchipip.serdes.WithSerialTLMem(size = (1 << 30) * 4L) ++ // Configure the off-chip memory accessible over serial-tl as backing memory + new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( // 1 serial tilelink port + manager = Some(testchipip.serdes.SerialTLManagerParams( // port acts as a manager of offchip memory + memParams = Seq(testchipip.serdes.ManagerRAMParams( // 4 GB of off-chip memory + address = BigInt("80000000", 16), + size = BigInt("100000000", 16) + )), + isMemoryDevice = true + )), + client = Some(testchipip.serdes.SerialTLClientParams()), // Allow an external manager to probe this chip + phyParams = testchipip.serdes.ExternalSyncSerialParams(width=4) // 4-bit bidir interface, sync'd to an external clock + ))) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel @@ -60,10 +70,16 @@ class ChipBringupHostConfig extends Config( //============================= // Setup the SerialTL side on the bringup device //============================= - new testchipip.serdes.WithSerialTLWidth(4) ++ // match width with the chip - new testchipip.serdes.WithSerialTLMem(base = 0x0, size = 0x80000000L, // accessible memory of the chip that doesn't come from the tethered host - idBits = 4, isMainMemory = false) ++ // This assumes off-chip mem starts at 0x8000_0000 - new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock + new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( + manager = Some(testchipip.serdes.SerialTLManagerParams( + memParams = Seq(testchipip.serdes.ManagerRAMParams( // Bringup platform can access all memory from 0 to DRAM_BASE + address = BigInt("00000000", 16), + size = BigInt("80000000", 16) + )) + )), + client = Some(testchipip.serdes.SerialTLClientParams()), // Allow chip to access this device's memory (DRAM) + phyParams = testchipip.serdes.InternalSyncSerialParams(width=4, freqMHz = 75) // bringup platform provides the clock + ))) ++ //============================ // Setup bus topology on the bringup system diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index d9e37918..9eeabecf 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.util.{PlusArg} import freechips.rocketchip.subsystem.{CacheBlockBytes} import freechips.rocketchip.devices.debug.{SimJTAG} import freechips.rocketchip.jtag.{JTAGIO} -import testchipip.serdes.{SerialTLKey, LocallySyncSerialIO, ExternallySyncSerialIO} +import testchipip.serdes._ import testchipip.uart.{UARTAdapter} import testchipip.dram.{SimDRAM} import testchipip.tsi.{TSIHarness, SimTSI, SerialRAM} @@ -48,23 +48,26 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { // Figure out which clock drives the harness TLSerdes, based on the port type val serial_ram_clock = dut.serial_tl_pad match { - case io: LocallySyncSerialIO => io.clock_out - case io: ExternallySyncSerialIO => clock + case io: InternalSyncSerialIO => io.clock_out + case io: ExternalSyncSerialIO => clock + } + dut.serial_tl_pad match { + case io: ExternalSyncSerialIO => io.clock_in := clock + case io: InternalSyncSerialIO => } - withClockAndReset(serial_ram_clock, reset) { - dut.serial_tl_pad match { - case io: ExternallySyncSerialIO => io.clock_in := clock - case io: LocallySyncSerialIO => + dut.serial_tl_pad match { + case pad: DecoupledSerialIO => { + withClockAndReset(serial_ram_clock, reset) { + // SerialRAM implements the memory regions the chip expects + val ram = Module(LazyModule(new SerialRAM(lazyDut.system.serdessers(0), p(SerialTLKey)(0))).module) + ram.io.ser.in <> pad.out + pad.in <> ram.io.ser.out + + // Allow TSI to master the chip + io.success := SimTSI.connect(ram.io.tsi, serial_ram_clock, reset) + } } - - // SerialRAM implements the memory regions the chip expects - val ram = Module(LazyModule(new SerialRAM(lazyDut.system.serdessers(0), p(SerialTLKey)(0))).module) - ram.io.ser.in <> dut.serial_tl_pad.out - dut.serial_tl_pad.in <> ram.io.ser.out - - // Allow TSI to master the chip - io.success := SimTSI.connect(ram.io.tsi, serial_ram_clock, reset) } // JTAG diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 128cae0e..a29cf5c0 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -211,8 +211,8 @@ class WithSerialTLTiedOff extends HarnessBinder({ case io: DecoupledSerialIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare; } port.io match { - case io: LocallySyncSerialIO => - case io: ExternallySyncSerialIO => io.clock_in := false.B.asClock + case io: InternalSyncSerialIO => + case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock } } }) @@ -220,8 +220,8 @@ class WithSerialTLTiedOff extends HarnessBinder({ class WithSimTSIOverSerialTL extends HarnessBinder({ case (th: HasHarnessInstantiators, port: SerialTLPort) => { port.io match { - case io: LocallySyncSerialIO => - case io: ExternallySyncSerialIO => io.clock_in := false.B.asClock + case io: InternalSyncSerialIO => + case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock } port.io match { @@ -229,8 +229,8 @@ class WithSimTSIOverSerialTL extends HarnessBinder({ // If the port is locally synchronous (provides a clock), drive everything with that clock // Else, drive everything with the harnes clock val clock = port.io match { - case io: LocallySyncSerialIO => io.clock_out - case io: ExternallySyncSerialIO => th.harnessBinderClock + case io: InternalSyncSerialIO => io.clock_out + case io: ExternalSyncSerialIO => th.harnessBinderClock } withClock(clock) { val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module) diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala index d89d2d98..e159e345 100644 --- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala @@ -60,14 +60,14 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p (p0: SerialTLPort) => p0.portId == chip0portId, (p1: SerialTLPort) => p1.portId == chip1portId, (th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => { - def connectDecoupledSyncSerialIO(clkSource: LocallySyncSerialIO, clkSink: ExternallySyncSerialIO) = { + def connectDecoupledSyncSerialIO(clkSource: InternalSyncSerialIO, clkSink: ExternalSyncSerialIO) = { clkSink.clock_in := clkSource.clock_out clkSink.in <> clkSource.out clkSource.in <> clkSink.out } (p0.io, p1.io) match { - case (io0: LocallySyncSerialIO , io1: ExternallySyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1) - case (io0: ExternallySyncSerialIO, io1: LocallySyncSerialIO) => connectDecoupledSyncSerialIO(io1, io0) + case (io0: InternalSyncSerialIO, io1: ExternalSyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1) + case (io0: ExternalSyncSerialIO, io1: InternalSyncSerialIO) => connectDecoupledSyncSerialIO(io1, io0) } } ) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 25ae6668..1cb365bd 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -15,7 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters} import freechips.rocketchip.util.{ResetCatchAndSync} import sifive.blocks.devices.uart._ -import testchipip.serdes.{ExternallySyncSerialIO} +import testchipip.serdes.{ExternalSyncSerialIO} import testchipip.tsi.{SerialRAM} import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} @@ -69,7 +69,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({ case (th: FireSim, port: SerialTLPort) => { port.io match { - case io: ExternallySyncSerialIO => { + case io: ExternalSyncSerialIO => { io.clock_in := th.harnessBinderClock val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module) ram.io.ser.in <> io.out diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 9f5f7ef6..eb092944 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -260,7 +260,7 @@ class FireSimSmallSystemConfig extends Config( new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)), - width = 32 + phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32) ))) ++ new testchipip.iceblk.WithBlockDevice ++ new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++ diff --git a/generators/testchipip b/generators/testchipip index e53f78aa..9011ac85 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit e53f78aa189c0cf7e0d3a9b08b44222ca05ab160 +Subproject commit 9011ac8530f8186e013409f0e2d65f54b2b512d4