From 1a6b34696eb74524485d7aee33fa2a3c50c9c199 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 11 May 2023 10:43:16 -0700 Subject: [PATCH] Set a more realistic 500 MHz uncore clock: --- .../chipyard/src/main/scala/config/AbstractConfig.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 02ab9b5a..6d243d5f 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -56,8 +56,8 @@ class AbstractConfig extends Config( new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) - new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus - new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus + new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus + new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ // Default 2 memory channels new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port