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FIX: fix Arty FPGA reset signal (#1257)

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-T.K.-
2022-12-07 19:34:35 -08:00
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parent 6929ea0165
commit 1b7457d2fc
1 changed files with 1 additions and 1 deletions
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fpga/src/main/scala/arty/TestHarness.scala
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@@ -17,7 +17,7 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
// Convert harness resets from Bool to Reset type. // Convert harness resets from Bool to Reset type.
val hReset = Wire(Reset()) val hReset = Wire(Reset())
hReset := ck_rst hReset := ~ck_rst
val dReset = Wire(AsyncReset()) val dReset = Wire(AsyncReset())
dReset := reset_core.asAsyncReset dReset := reset_core.asAsyncReset