FIX: fix Arty FPGA reset signal (#1257)

2022-12-07 19:34:35 -08:00
parent 6929ea0165
commit 1b7457d2fc
1 changed files with 1 additions and 1 deletions
--- a/fpga/src/main/scala/arty/TestHarness.scala
+++ b/fpga/src/main/scala/arty/TestHarness.scala
@@ -17,7 +17,7 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell

  // Convert harness resets from Bool to Reset type.
  val hReset = Wire(Reset())
-  hReset := ck_rst
+  hReset := ~ck_rst

  val dReset = Wire(AsyncReset())
  dReset := reset_core.asAsyncReset