From 1ce67a0997069db0438c4687874f42bf05cd0dbd Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 10 Jan 2022 09:09:21 -0800 Subject: [PATCH] Add WithSystemBusWidth fragment (#1071) --- .../src/main/scala/config/fragments/SubsystemFragments.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index 47f24cdc..534259ab 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -1,10 +1,13 @@ package chipyard.config import freechips.rocketchip.config.{Config} -import freechips.rocketchip.subsystem.{BankedL2Key, CoherenceManagerWrapper} +import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper} // Replaces the L2 with a broadcast manager for maintaining coherence class WithBroadcastManager extends Config((site, here, up) => { case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) }) +class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => { + case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8) +})