From 1d85dc32a07cc391ee1763f71eef17ba14f2b858 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 27 Aug 2019 12:00:50 -0700 Subject: [PATCH] Use HasHierarchicalBusTopology mixin --- .../example/src/main/scala/System.scala | 20 +------------------ 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/generators/example/src/main/scala/System.scala b/generators/example/src/main/scala/System.scala index 1c62bf51..3b39ff80 100644 --- a/generators/example/src/main/scala/System.scala +++ b/generators/example/src/main/scala/System.scala @@ -22,6 +22,7 @@ import freechips.rocketchip.util.{DontTouch} * Base top with periphery devices and ports, and a BOOM + Rocket subsystem */ class System(implicit p: Parameters) extends Subsystem + with HasHierarchicalBusTopology with HasAsyncExtInterrupts with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MMIOPort @@ -29,25 +30,6 @@ class System(implicit p: Parameters) extends Subsystem with HasPeripheryBootROM { override lazy val module = new SystemModule(this) - - // The sbus masters the cbus; here we convert TL-UH -> TL-UL - sbus.crossToBus(cbus, NoCrossing) - - // The cbus masters the pbus; which might be clocked slower - cbus.crossToBus(pbus, SynchronousCrossing()) - - // The fbus masters the sbus; both are TL-UH or TL-C - FlipRendering { implicit p => - sbus.crossFromBus(fbus, SynchronousCrossing()) - } - - // The sbus masters the mbus; here we convert TL-C -> TL-UH - private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) - private val (in, out, halt) = coherenceManager(this) - if (nBanks != 0) { - sbus.coupleTo("coherence_manager") { in :*= _ } - mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } - } } /**