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Add LLC bufExterior comment

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This commit is contained in:
Jerry Zhao
2023-11-16 22:06:34 -08:00
committed by GitHub
parent ab4c4d809c
commit 1e2667e0bc
1 changed files with 2 additions and 1 deletions
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3
generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
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@@ -18,11 +18,12 @@ class WithDTSTimebase(freqMHz: BigInt) extends Config((site, here, up) => {
case DTSTimebase => freqMHz case DTSTimebase => freqMHz
}) })
// Adds buffers on the interior of the inclusive L2, to improve PD // Adds buffers on the interior of the inclusive LLC, to improve PD
class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => { class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer) case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer)
}) })
// Adds buffers on the exterior of the inclusive LLC, to improve PD
class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => { class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer) case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer)
}) })