diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index ad643deb..954c104c 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -15,7 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import sifive.blocks.devices.uart._
 
-import testchipip._
+import testchipip.tsi.{SerialRAM}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
 
 import junctions.{NastiKey, NastiParameters}
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index 944fe9cf..9f5f7ef6 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -13,7 +13,8 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams}
 import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
 import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing}
-import testchipip.{BlockDeviceKey, BlockDeviceConfig, TracePortKey, TracePortParams}
+import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig}
+import testchipip.cosim.{TracePortKey, TracePortParams}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import scala.math.{min, max}
 
@@ -101,7 +102,7 @@ class WithFireSimDesignTweaks extends Config(
   // Required: Bake in the default FASED memory model
   new WithDefaultMemModel ++
   // Optional: reduce the width of the Serial TL interface
-  new testchipip.WithSerialTLWidth(4) ++
+  new testchipip.serdes.WithSerialTLWidth(4) ++
   // Required*: Scale default baud rate with periphery bus frequency
   new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
   // Optional: Adds IO to attach tracerV bridges
@@ -109,7 +110,7 @@ class WithFireSimDesignTweaks extends Config(
   // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1)
   new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
   // Optional: Removing this will require using an initramfs under linux
-  new testchipip.WithBlockDevice
+  new testchipip.iceblk.WithBlockDevice
 )
 
 // Tweaks to modify target clock frequencies / crossings to legacy firesim defaults
@@ -151,7 +152,7 @@ class WithFireSimConfigTweaks extends Config(
 class WithMinimalFireSimHighPerfConfigTweaks extends Config(
   new WithFireSimHighPerfClocking ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
-  new testchipip.WithMbusScratchpad ++
+  new testchipip.soc.WithMbusScratchpad ++
   new WithMinimalFireSimDesignTweaks
 )
 
@@ -161,8 +162,8 @@ class WithMinimalFireSimHighPerfConfigTweaks extends Config(
 class WithMinimalAndBlockDeviceFireSimHighPerfConfigTweaks extends Config(
   new WithFireSimHighPerfClocking ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++ // removes mem port for FASEDBridge to match against
-  new testchipip.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model
-  new testchipip.WithBlockDevice(true) ++ // add in block device
+  new testchipip.soc.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model
+  new testchipip.iceblk.WithBlockDevice(true) ++ // add in block device
   new WithMinimalFireSimDesignTweaks
 )
 
@@ -257,11 +258,11 @@ class FireSimSmallSystemConfig extends Config(
   new WithoutClockGating ++
   new WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
-  new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams(
-    client = Some(testchipip.SerialTLClientParams(idBits = 4)),
+  new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(
+    client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)),
     width = 32
   ))) ++
-  new testchipip.WithBlockDevice ++
+  new testchipip.iceblk.WithBlockDevice ++
   new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++
   new chipyard.RocketConfig)
@@ -339,7 +340,7 @@ class FireSim16LargeBoomConfig extends Config(
 class FireSimNoMemPortConfig extends Config(
   new WithDefaultFireSimBridges ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
-  new testchipip.WithMbusScratchpad ++
+  new testchipip.soc.WithMbusScratchpad ++
   new WithFireSimConfigTweaks ++
   new chipyard.RocketConfig)
 
diff --git a/sims/firesim b/sims/firesim
index 73fe6a51..e9758935 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 73fe6a51b28a2dbbe3f307bdbc6ba2407b311a27
+Subproject commit e975893595129c2682a72fb7e5898273fcc2d071