From 1ee45b55da1095914f0f8afe4e7f3b49507cbaab Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 11 Feb 2023 12:58:43 -0800 Subject: [PATCH] Add new PeripheralDeviceConfigs --- .../config/PeripheralDeviceConfigs.scala | 65 +++++++++++++++++++ .../src/main/scala/config/RocketConfigs.scala | 58 ----------------- 2 files changed, 65 insertions(+), 58 deletions(-) create mode 100644 generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala new file mode 100644 index 00000000..37e4570a --- /dev/null +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -0,0 +1,65 @@ +package chipyard + +import freechips.rocketchip.config.{Config} +import freechips.rocketchip.diplomacy.{AsynchronousCrossing} + +// --------------------------------------------------------- +// Configs which add non-default peripheral devices or ports +// --------------------------------------------------------- + +class LargeSPIFlashROMRocketConfig extends Config( + new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) + new chipyard.config.WithSPIFlash ++ // add the SPI flash controller + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +class SmallSPIFlashRocketConfig extends Config( + new chipyard.harness.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable) + new chipyard.config.WithSPIFlash(0x100000) ++ // add the SPI flash controller (1 MiB) + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +class SimBlockDeviceRocketConfig extends Config( + new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice + new testchipip.WithBlockDevice ++ // add block-device module to peripherybus + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +class BlockDeviceModelRocketConfig extends Config( + new chipyard.harness.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel + new testchipip.WithBlockDevice ++ // add block-device module to periphery bus + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +// DOC include start: GPIORocketConfig +class GPIORocketConfig extends Config( + new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) +// DOC include end: GPIORocketConfig + +class LoopbackNICRocketConfig extends Config( + new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback + new icenet.WithIceNIC ++ // add an IceNIC + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +class MMIORocketConfig extends Config( + new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port + new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +class LBWIFRocketConfig extends Config( + new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +// DOC include start: DmiRocket +class dmiRocketConfig extends Config( + new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) +// DOC include end: DmiRocket diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 57971d9a..c6f5ca22 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -21,51 +21,11 @@ class TinyRocketConfig extends Config( new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core new chipyard.config.AbstractConfig) -// DOC include start: DmiRocket -class dmiRocketConfig extends Config( - new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial - new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) -// DOC include end: DmiRocket - - -class LargeSPIFlashROMRocketConfig extends Config( - new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) - new chipyard.config.WithSPIFlash ++ // add the SPI flash controller - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) - -class SmallSPIFlashRocketConfig extends Config( - new chipyard.harness.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable) - new chipyard.config.WithSPIFlash(0x100000) ++ // add the SPI flash controller (1 MiB) - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) - class SimAXIRocketConfig extends Config( new chipyard.harness.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) -class SimBlockDeviceRocketConfig extends Config( - new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice - new testchipip.WithBlockDevice ++ // add block-device module to peripherybus - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) - -class BlockDeviceModelRocketConfig extends Config( - new chipyard.harness.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel - new testchipip.WithBlockDevice ++ // add block-device module to periphery bus - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) - -// DOC include start: GPIORocketConfig -class GPIORocketConfig extends Config( - new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) -// DOC include end: GPIORocketConfig - class QuadRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles) new chipyard.config.AbstractConfig) @@ -85,12 +45,6 @@ class GB1MemoryRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) -class LoopbackNICRocketConfig extends Config( - new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback - new icenet.WithIceNIC ++ // add an IceNIC - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) - // DOC include start: l1scratchpadrocket class ScratchpadOnlyRocketConfig extends Config( new testchipip.WithSerialPBusMem ++ @@ -122,12 +76,6 @@ class MbusScratchpadRocketConfig extends Config( new chipyard.config.AbstractConfig) // DOC include end: mbusscratchpadrocket -class MMIORocketConfig extends Config( - new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port - new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) - class MulticlockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Frequency specifications @@ -148,12 +96,6 @@ class TestChipMulticlockRocketConfig extends Config( new chipyard.config.WithTestChipBusFreqs ++ new chipyard.config.AbstractConfig) -class LBWIFRocketConfig extends Config( - new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory - new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) - // DOC include start: MulticlockAXIOverSerialConfig class MulticlockAXIOverSerialConfig extends Config( new chipyard.config.WithSystemBusFrequencyAsDefault ++