wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

[skip ci] Makefile typo

Browse Source
This commit is contained in:
Harrison Liew
2023-02-02 22:33:49 -08:00
committed by abejgonzalez
parent a6342ced21
commit 223995fb4e
1 changed files with 3 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
vlsi/Makefile
View File

@@ -58,13 +58,8 @@ endif
ifneq ($(CUSTOM_VLOG), ) ifneq ($(CUSTOM_VLOG), )
VLSI_RTL = $(CUSTOM_VLOG) VLSI_RTL = $(CUSTOM_VLOG)
else else
# This one-liner does a few things. Line-by-line: VLSI_RTL = $(shell cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST)) \
# 1. concatenates the .top.f and .bb.f files and uniquifies them $(TOP_SMEMS_FILE) $(build_dir)/EICG_wrapper.v
# 2. removes all harness blackboxes with DPI calls (SimJTAG, etc.)
# 3. append EICG_wrapper.v and the compiled memories
VLSI_RTL = $(shell cat $(TOP_MODS_FILELIST) $(BB_MODS_FILELIST) | sort | uniq | \
rev | sed -E 's/cc(.*)/c\1/g' | uniq -s 1 | sed '/c\./d' | rev) \
$(build_dir)/EICG_wrapper.v $(TOP_SMEMS_FILE)
endif endif
.PHONY: default .PHONY: default