diff --git a/.gitmodules b/.gitmodules index 0e8194d4..da4aaf12 100644 --- a/.gitmodules +++ b/.gitmodules @@ -129,4 +129,10 @@ url = https://github.com/ucb-bar/shuttle.git [submodule "generators/bar-fetchers"] path = generators/bar-fetchers - url = https://github.com/ucb-bar/bar-fetchers.git \ No newline at end of file + url = https://github.com/ucb-bar/bar-fetchers.git +[submodule "tools/fixedpoint"] + path = tools/fixedpoint + url = https://github.com/ucb-bar/fixedpoint.git +[submodule "generators/hardfloat"] + path = generators/hardfloat + url = https://github.com/ucb-bar/berkeley-hardfloat.git diff --git a/build.sbt b/build.sbt index e39fc703..76147789 100644 --- a/build.sbt +++ b/build.sbt @@ -82,7 +82,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => new Group(test.name, Seq(test), SubProcess(options)) } toSeq -val chiselVersion = "3.5.6" +val chiselVersion = "3.6.0" lazy val chiselSettings = Seq( libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion, @@ -91,16 +91,11 @@ lazy val chiselSettings = Seq( addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)) -val chiselTestVersion = "2.5.1" - -lazy val chiselTestSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel-iotesters" % chiselTestVersion)) - // Subproject definitions begin // -- Rocket Chip -- -// Rocket-chip dependencies (subsumes making RC a RootProject) -lazy val hardfloat = (project in rocketChipDir / "hardfloat") +lazy val hardfloat = freshProject("hardfloat", rocketChipDir / "hardfloat/hardfloat") .settings(chiselSettings) .dependsOn(midasTargetUtils) .settings(commonSettings) @@ -124,8 +119,9 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir) .settings(chiselSettings) .settings( libraryDependencies ++= Seq( + "com.lihaoyi" %% "mainargs" % "0.5.0", "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "org.json4s" %% "json4s-jackson" % "3.6.6", + "org.json4s" %% "json4s-jackson" % "4.0.5", "org.scalatest" %% "scalatest" % "3.2.0" % "test", "org.scala-graph" %% "graph-core" % "1.13.5" ) @@ -152,7 +148,7 @@ lazy val testchipip = (project in file("generators/testchipip")) lazy val chipyard = (project in file("generators/chipyard")) .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches - dsptools, `rocket-dsp-utils`, + dsptools, rocket_dsp_utils, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, constellation, mempress, barf, shuttle) .settings(libraryDependencies ++= rocketLibDeps.value) @@ -166,7 +162,6 @@ lazy val chipyard = (project in file("generators/chipyard")) lazy val mempress = (project in file("generators/mempress")) .dependsOn(rocketchip, midasTargetUtils) .settings(libraryDependencies ++= rocketLibDeps.value) - .settings(chiselTestSettings) .settings(commonSettings) lazy val barf = (project in file("generators/bar-fetchers")) @@ -180,7 +175,7 @@ lazy val constellation = (project in file("generators/constellation")) .settings(commonSettings) lazy val fft_generator = (project in file("generators/fft-generator")) - .dependsOn(rocketchip, `rocket-dsp-utils`) + .dependsOn(rocketchip, rocket_dsp_utils) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) @@ -199,7 +194,7 @@ lazy val hwacha = (project in file("generators/hwacha")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val boom = (project in file("generators/boom")) +lazy val boom = freshProject("boom", file("generators/boom")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) @@ -227,13 +222,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) lazy val sha3 = (project in file("generators/sha3")) .dependsOn(rocketchip, midasTargetUtils) .settings(libraryDependencies ++= rocketLibDeps.value) - .settings(chiselTestSettings) .settings(commonSettings) lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) - .settings(chiselTestSettings) .settings(commonSettings) lazy val nvdla = (project in file("generators/nvdla")) @@ -247,18 +240,22 @@ lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "io lazy val tapeout = (project in file("./tools/barstools/")) .settings(chiselSettings) - .settings(chiselTestSettings) + .settings(commonSettings) + +lazy val fixedpoint = (project in file("./tools/fixedpoint/")) + .settings(chiselSettings) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) + .dependsOn(fixedpoint) .settings( chiselSettings, - chiselTestSettings, commonSettings, libraryDependencies ++= Seq( + "edu.berkeley.cs" %% "chiseltest" % "0.6.0", "org.scalatest" %% "scalatest" % "3.2.+" % "test", - "org.typelevel" %% "spire" % "0.17.0", - "org.scalanlp" %% "breeze" % "1.1", + "org.typelevel" %% "spire" % "0.18.0", + "org.scalanlp" %% "breeze" % "2.1.0", "junit" % "junit" % "4.13" % "test", "org.scalacheck" %% "scalacheck" % "1.14.3" % "test", )) @@ -267,7 +264,7 @@ lazy val cde = (project in file("tools/cde")) .settings(commonSettings) .settings(Compile / scalaSource := baseDirectory.value / "cde/src/chipsalliance/rocketchip") -lazy val `rocket-dsp-utils` = freshProject("rocket-dsp-utils", file("./tools/rocket-dsp-utils")) +lazy val rocket_dsp_utils = freshProject("rocket-dsp-utils", file("./tools/rocket-dsp-utils")) .dependsOn(rocketchip, cde, dsptools) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/SiFive-Generators.rst index c3840297..73bb5b49 100644 --- a/docs/Generators/SiFive-Generators.rst +++ b/docs/Generators/SiFive-Generators.rst @@ -11,24 +11,18 @@ Last-Level Cache Generator To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section. -Peripheral Devices -------------------- +Peripheral Devices Overview +---------------------------- ``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more. These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well. -To integrate one of these devices in your SoC, you will need to define a custom config fragment with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following config fragment to set the GPIO address to ``0x10012000``. This address is the start address for the GPIO configuration registers. - -.. literalinclude:: ../../generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala - :language: scala - :start-after: DOC include start: gpio config fragment - :end-before: DOC include end: gpio config fragment +All the peripheral blocks comes with a default memory address that would not collide with each other, but if integrating multiple duplicated blocks in the SoC is needed, you will need to explicitly specify an approriate memory address for that device. Additionally, if the device requires top-level IOs, you will need to define a config fragment to change the top-level configuration of your SoC. When adding a top-level IO, you should also be aware of whether it interacts with the test-harness. This example instantiates a top-level module with include GPIO ports, and then ties-off the GPIO port inputs to 0 (``false.B``). - Finally, you add the relevant config fragment to the SoC config. For example: .. literalinclude:: ../../generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -36,4 +30,187 @@ Finally, you add the relevant config fragment to the SoC config. For example: :start-after: DOC include start: GPIORocketConfig :end-before: DOC include end: GPIORocketConfig -Some of the devices in ``sifive-blocks`` (such as GPIO) may already have pre-defined config fragments within the Chipyard example project. You may be able to use these config fragments directly, but you should be aware of their addresses within the SoC address map. + +General Purpose I/Os (GPIO) Device +---------------------------------- + +GPIO device is a periphery device provided by ``sifive-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers. + + +GPIO main features +~~~~~~~~~~~~~~~~~~~~~~~ + +* Output states: push-pull or open drain with optional pull-up/down resistors + +* Output data from output value register (GPIOx_OUTPUT_VAL) or peripheral (alternate function output) + +* 3-bit drive strength selection for each I/O + +* Input states: floating, pull-up, or pull-down + +* Input data to input value register (GPIOx_INPUT_VAL) or peripheral (alternate function input) + +* Alternate function selection registers + +* Bit invert register (GPIOx_OUTPUT_XOR) for fast output inversion + + +Including GPIO in the SoC +~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code-block:: scala + + class ExampleChipConfig extends Config( + // ... + + // ================================== + // Set up Memory Devices + // ================================== + // ... + + // Peripheral section + new chipyard.config.WithGPIO(address = 0x10010000, width = 32) ++ + + // ... + ) + + +Universal Asynchronous Receiver/Transmitter (UART) Device +---------------------------------------------------------- + +UART device is a periphery device provided by ``sifive-blocks``. The UART offers a flexible means to perform Full-duplex data exchange with external devices. A very wide range of baud rates can be achieved through a fractional baud rate generator. The UART peripheral does not support other modem control signals, or synchronous serial data transfers. + + +UART main features +~~~~~~~~~~~~~~~~~~~~~~~ + +* Full-duplex asynchronous communication + +* Baud rate generator systems + +* 16× Rx oversampling with 2/3 majority voting per bit + +* Two internal FIFOs for transmit and receive data with programmable watermark interrupts + +* A common programmable transmit and receive baud rate + +* Configurable stop bits (1 or 2 stop bits) + +* Separate enable bits for transmitter and receiver + +* Interrupt sources with flags + +* Configurable hardware flow control signals + + +Including UART in the SoC +~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code-block:: scala + + class ExampleChipConfig extends Config( + // ... + + // ================================== + // Set up Memory Devices + // ================================== + // ... + + // Peripheral section + new chipyard.config.WithUART(address = 0x10020000, baudrate = 115200) ++ + + // ... + ) + +Inter-Integrated Circuit (I2C) Interface Device +------------------------------------------------- + +I2C device is a periphery device provided by ``sifive-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+). + + +I2C main features +~~~~~~~~~~~~~~~~~~~~~~~ + +* I2C bus specification compatibility: + + * Slave and master modes + + * Multimaster capability + + * Standard-mode (up to 100 kHz) + + * Fast-mode (up to 400 kHz) + + * Fast-mode Plus (up to 1 MHz) + + * 7-bit addressing mode + + +Including I2C in the SoC +~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code-block:: scala + + class ExampleChipConfig extends Config( + // ... + + // ================================== + // Set up Memory Devices + // ================================== + // ... + + // Peripheral section + new chipyard.config.WithI2C(address = 0x10040000) ++ + + // ... + ) + + +Serial Peripheral Interface (SPI) Device +------------------------------------------------- + +SPI device is a periphery device provided by ``sifive-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol. + +The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master and in this case it provides the communication clock (SCLK) to the external slave device. + + +SPI main features +~~~~~~~~~~~~~~~~~~~~~~~ + +* Master operation + +* Full-duplex synchronous transfers + +* 4 to 16-bit data size selection + +* Master mode baud rate prescalers up to fPCLK/2 + +* NSS management by hardware or software + +* Programmable clock polarity and phase + +* Programmable data order with MSB-first or LSB-first shifting + +* Dedicated transmission and reception flags with interrupt capability + +* Two 32-bit embedded Rx and Tx FIFOs with DMA capability + + +Including SPI in the SoC +~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code-block:: scala + + class ExampleChipConfig extends Config( + // ... + + // ================================== + // Set up Memory Devices + // ================================== + // ... + + // Peripheral section + new chipyard.config.WithSPI(address = 0x10031000) ++ + + // ... + ) diff --git a/fpga/fpga-shells b/fpga/fpga-shells index b6cd1bb7..1bdd4362 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit b6cd1bb7fe35bb7a44b6fe5a0d88d1293d7a3bc9 +Subproject commit 1bdd436287cde561a7b9e426670ec23c28752e28 diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 306a1743..2d524fe3 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -25,5 +25,11 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell def referenceClock = clock_32MHz def referenceReset = hReset + dut_jtag_TCK := DontCare + dut_jtag_TMS := DontCare + dut_jtag_TDI := DontCare + dut_jtag_TDO := DontCare + dut_jtag_reset := DontCare + instantiateChipTops() } diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala index 2b4b5047..008e2399 100644 --- a/fpga/src/main/scala/vc707/TestHarness.scala +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -90,7 +90,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators { val vc707Outer = _outer - val reset = IO(Input(Bool())) + val reset = IO(Input(Bool())).suggestName("reset") _outer.xdc.addBoardPin(reset, "reset") val resetIBUF = Module(new IBUF) @@ -108,6 +108,8 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul _outer.pllReset := (resetIBUF.io.O || powerOnReset || ereset) + _outer.ledModule.foreach(_ := DontCare) + // reset setup val hReset = Wire(Reset()) hReset := _outer.dutClock.in.head._1.reset diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 850b7f62..6bffc9a7 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -93,7 +93,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators { val vcu118Outer = _outer - val reset = IO(Input(Bool())) + val reset = IO(Input(Bool())).suggestName("reset") _outer.xdc.addPackagePin(reset, "L19") _outer.xdc.addIOStandard(reset, "LVCMOS12") diff --git a/generators/bar-fetchers b/generators/bar-fetchers index 3a33d818..a5bd985d 160000 --- a/generators/bar-fetchers +++ b/generators/bar-fetchers @@ -1 +1 @@ -Subproject commit 3a33d818aefe5444aa27fc1557008f747538d2cc +Subproject commit a5bd985d29b07940e326d78964b370fa1cefec71 diff --git a/generators/boom b/generators/boom index 1a153d49..247ed490 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 1a153d4974977a2d5f8baa9b4de51b3337d230fe +Subproject commit 247ed4903d731d303e44f312999cc810e4bd7244 diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc index bc065860..8f2b28a3 100644 --- a/generators/chipyard/src/main/resources/csrc/cospike.cc +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -42,6 +42,7 @@ extern std::map backing_mem_data; typedef struct system_info_t { std::string isa; + int vlen; int pmpregions; uint64_t mem0_base; uint64_t mem0_size; @@ -79,9 +80,9 @@ std::set magic_addrs; cfg_t* cfg; std::vector> read_override_devices; -static std::vector> make_mems(const std::vector &layout) +static std::vector> make_mems(const std::vector &layout) { - std::vector> mems; + std::vector> mems; mems.reserve(layout.size()); for (const auto &cfg : layout) { mems.push_back(std::make_pair(cfg.get_base(), new mem_t(cfg.get_size()))); @@ -89,7 +90,7 @@ static std::vector> make_mems(const std::vectorisa = std::string(isa) + "_zicntr"; + info->vlen = vlen; info->priv = std::string(priv); info->pmpregions = pmpregions; info->mem0_base = mem0_base; @@ -133,11 +135,12 @@ extern "C" void cospike_cosim(long long int cycle, for (int i = 0; i < info->nharts; i++) hartids.push_back(i); + std::string visa = "vlen:" + std::to_string(info->vlen ? info->vlen : 128) + ",elen:64"; cfg = new cfg_t(std::make_pair(0, 0), nullptr, info->isa.c_str(), info->priv.c_str(), - "vlen:128,elen:64", + visa.c_str(), false, endianness_little, info->pmpregions, @@ -147,7 +150,7 @@ extern "C" void cospike_cosim(long long int cycle, 0 ); - std::vector> mems = make_mems(cfg->mem_layout()); + std::vector> mems = make_mems(cfg->mem_layout()); size_t default_boot_rom_size = 0x10000; size_t default_boot_rom_addr = 0x10000; @@ -420,7 +423,8 @@ extern "C" void cospike_cosim(long long int cycle, bool scalar_wb = false; bool vector_wb = false; uint32_t vector_cnt = 0; - + std::vector vector_rds; + for (auto ®write : log) { //TODO: scaling to multi issue reads? @@ -446,15 +450,16 @@ extern "C" void cospike_cosim(long long int cycle, lr_read || (tohost_addr && mem_read_addr == tohost_addr) || (fromhost_addr && mem_read_addr == fromhost_addr))); + //COSPIKE_PRINTF("register write type %d\n", type); // check the type is compliant with writeback first if ((type == 0 || type == 1)) scalar_wb = true; if (type == 2) { + vector_rds.push_back(rd); vector_wb = true; } if (type == 3) continue; - if ((rd != 0 && type == 0) || type == 1) { // Override reads from some CSRs uint64_t csr_addr = (insn >> 20) & 0xfff; @@ -496,5 +501,8 @@ extern "C" void cospike_cosim(long long int cycle, // exit(-1); // } } + for (auto &a : vector_rds) { + COSPIKE_PRINTF("vector writeback to v%d\n", a); + } } } diff --git a/generators/chipyard/src/main/resources/vsrc/cospike.v b/generators/chipyard/src/main/resources/vsrc/cospike.v index b95670a9..33b8ecdd 100644 --- a/generators/chipyard/src/main/resources/vsrc/cospike.v +++ b/generators/chipyard/src/main/resources/vsrc/cospike.v @@ -1,75 +1,77 @@ import "DPI-C" function void cospike_set_sysinfo( - input string isa, - input string priv, - input int pmpregions, - input longint mem0_base, - input longint mem0_size, - input int nharts, - input string bootrom - ); + input string isa, + input int vlen, + input string priv, + input int pmpregions, + input longint mem0_base, + input longint mem0_size, + input int nharts, + input string bootrom + ); import "DPI-C" function void cospike_cosim(input longint cycle, input longint hartid, - input bit has_wdata, - input bit valid, - input longint iaddr, - input int insn, - input bit raise_exception, - input bit raise_interrupt, - input longint cause, - input longint wdata, - input int priv - ); + input bit has_wdata, + input bit valid, + input longint iaddr, + input int insn, + input bit raise_exception, + input bit raise_interrupt, + input longint cause, + input longint wdata, + input int priv + ); module SpikeCosim #( - parameter ISA, - parameter PRIV, - parameter PMPREGIONS, - parameter MEM0_BASE, - parameter MEM0_SIZE, - parameter NHARTS, - parameter BOOTROM) ( - input clock, - input reset, + parameter ISA, + parameter PRIV, + parameter VLEN, + parameter PMPREGIONS, + parameter MEM0_BASE, + parameter MEM0_SIZE, + parameter NHARTS, + parameter BOOTROM) ( + input clock, + input reset, - input [63:0] cycle, + input [63:0] cycle, - input [63:0] hartid, + input [63:0] hartid, - input trace_0_valid, - input [63:0] trace_0_iaddr, - input [31:0] trace_0_insn, - input trace_0_exception, - input trace_0_interrupt, - input [63:0] trace_0_cause, - input trace_0_has_wdata, - input [63:0] trace_0_wdata, - input [2:0] trace_0_priv, + input trace_0_valid, + input [63:0] trace_0_iaddr, + input [31:0] trace_0_insn, + input trace_0_exception, + input trace_0_interrupt, + input [63:0] trace_0_cause, + input trace_0_has_wdata, + input [63:0] trace_0_wdata, + input [2:0] trace_0_priv, - input trace_1_valid, - input [63:0] trace_1_iaddr, - input [31:0] trace_1_insn, - input trace_1_exception, - input trace_1_interrupt, - input [63:0] trace_1_cause, - input trace_1_has_wdata, - input [63:0] trace_1_wdata, - input [2:0] trace_1_priv - ); + input trace_1_valid, + input [63:0] trace_1_iaddr, + input [31:0] trace_1_insn, + input trace_1_exception, + input trace_1_interrupt, + input [63:0] trace_1_cause, + input trace_1_has_wdata, + input [63:0] trace_1_wdata, + input [2:0] trace_1_priv + ); initial begin - cospike_set_sysinfo(ISA, PRIV, PMPREGIONS, MEM0_BASE, MEM0_SIZE, NHARTS, BOOTROM); + cospike_set_sysinfo(ISA, VLEN, PRIV, PMPREGIONS, MEM0_BASE, MEM0_SIZE, NHARTS, BOOTROM); end; always @(posedge clock) begin if (!reset) begin - if (trace_0_valid || trace_0_exception || trace_0_cause) begin - cospike_cosim(cycle, hartid, trace_0_has_wdata, trace_0_valid, trace_0_iaddr, - trace_0_insn, trace_0_exception, trace_0_interrupt, trace_0_cause, - trace_0_wdata, trace_0_priv); - end - if (trace_1_valid || trace_1_exception || trace_1_cause) begin + if (trace_0_valid || trace_0_exception || trace_0_cause) begin + cospike_cosim(cycle, hartid, trace_0_has_wdata, trace_0_valid, trace_0_iaddr, + trace_0_insn, trace_0_exception, trace_0_interrupt, trace_0_cause, + trace_0_wdata, trace_0_priv); + end + if (trace_1_valid || trace_1_exception || trace_1_cause) begin cospike_cosim(cycle, hartid, trace_1_has_wdata, trace_1_valid, trace_1_iaddr, trace_1_insn, trace_1_exception, trace_1_interrupt, trace_1_cause, trace_1_wdata, trace_1_priv); diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala index 182af91a..cf6cdbd1 100644 --- a/generators/chipyard/src/main/scala/Cospike.scala +++ b/generators/chipyard/src/main/scala/Cospike.scala @@ -14,6 +14,7 @@ import testchipip.TileTraceIO case class SpikeCosimConfig( isa: String, + vlen: Int, priv: String, pmpregions: Int, mem0_base: BigInt, @@ -25,6 +26,7 @@ case class SpikeCosimConfig( class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map( "ISA" -> StringParam(cfg.isa), + "VLEN" -> IntParam(cfg.vlen), "PRIV" -> StringParam(cfg.priv), "PMPREGIONS" -> IntParam(cfg.pmpregions), "MEM0_BASE" -> IntParam(cfg.mem0_base), diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 3c8fbeb0..b74d8f0e 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -225,6 +225,7 @@ class WithExtInterruptIOCells extends OverrideIOBinder({ val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey), abstractResetAsAsync = true) (Seq(port), cells) } else { + system.interrupts := DontCare // why do I have to drive this 0-wide wire??? (Nil, Nil) } } @@ -442,4 +443,13 @@ class WithDontTouchPorts extends OverrideIOBinder({ (system: DontTouch) => system.dontTouchPorts(); (Nil, Nil) }) - +class WithNMITiedOff extends ComposeIOBinder({ + (system: HasTilesModuleImp) => { + system.nmi.flatten.foreach { nmi => + nmi.rnmi := false.B + nmi.rnmi_interrupt_vector := 0.U + nmi.rnmi_exception_vector := 0.U + } + (Nil, Nil) + } +}) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 80b59efe..44235cbd 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -45,6 +45,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithNICIOPunchthrough ++ new chipyard.iobinders.WithTraceIOPunchthrough ++ new chipyard.iobinders.WithUARTTSIPunchthrough ++ + new chipyard.iobinders.WithNMITiedOff ++ // By default, punch out IOs to the Harness new chipyard.clocking.WithPassthroughClockGenerator ++ diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index f4bee2af..67b8fa7b 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -17,7 +17,7 @@ class ChipLikeRocketConfig extends Config( //================================== // Set up tiles //================================== - new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add rational crossings between RocketTile and uncore + new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(8, 3) ++ // Add async crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // 1 RocketTile //================================== diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 840185de..50f14bee 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -8,7 +8,7 @@ import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey, CLINTKey} import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} -import freechips.rocketchip.stage.phases.TargetDirKey +import chipyard.stage.phases.TargetDirKey import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{XLen} diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index b960251d..96e21611 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -141,5 +141,11 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule { //========================== require(system.uarts.size == 1) val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey)) + + + //========================== + // External interrupts (tie off) + //========================== + system.module.interrupts := DontCare } } diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index 3e315e65..01d72d24 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -3,7 +3,6 @@ package chipyard.example import chisel3._ -import chisel3.experimental.FixedPoint import chisel3.util._ import dspblocks._ import dsptools.numbers._ @@ -12,6 +11,8 @@ import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ +import fixedpoint._ +import fixedpoint.{fromIntToBinaryPoint, fromSIntToFixedPoint, fromUIntToFixedPoint} // FIR params case class GenericFIRParams( @@ -56,7 +57,7 @@ object GenericFIRIO { // A generic FIR filter // DOC include start: GenericFIR chisel -class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: Seq[T]) extends Module { +class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: => Seq[T]) extends Module { val io = IO(GenericFIRIO(genIn, genOut)) // Construct a vector of genericFIRDirectCells @@ -139,7 +140,7 @@ abstract class GenericFIRBlock[D, U, EO, EI, B<:Data, T<:Data:Ring] ( genIn: T, genOut: T, - coeffs: Seq[T] + coeffs: => Seq[T] )(implicit p: Parameters) extends DspBlock[D, U, EO, EI, B] { val streamNode = AXI4StreamIdentityNode() val mem = None @@ -175,7 +176,7 @@ class TLGenericFIRBlock[T<:Data:Ring] ( val genIn: T, val genOut: T, - coeffs: Seq[T] + coeffs: => Seq[T] )(implicit p: Parameters) extends GenericFIRBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle, T]( genIn, genOut, coeffs @@ -183,7 +184,7 @@ GenericFIRBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEd // DOC include end: TLGenericFIRBlock chisel // DOC include start: TLGenericFIRChain chisel -class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], params: GenericFIRParams)(implicit p: Parameters) +class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], params: GenericFIRParams)(implicit p: Parameters) extends TLChain(Seq( TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))(_), { implicit p: Parameters => @@ -201,7 +202,7 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem { val streamingFIR = LazyModule(new TLGenericFIRChain( genIn = FixedPoint(8.W, 3.BP), genOut = FixedPoint(8.W, 3.BP), - coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)), + coeffs = Seq(1.U.asFixedPoint(0.BP), 2.U.asFixedPoint(0.BP), 3.U.asFixedPoint(0.BP)), params = params)) pbus.coupleTo("streamingFIR") { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ } Some(streamingFIR) diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index ac50e52d..288655fc 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -365,6 +365,7 @@ class WithCospike extends ComposeHarnessBinder({ val tiles = chipyardSystem.tiles val cfg = SpikeCosimConfig( isa = tiles.headOption.map(_.isaDTS).getOrElse(""), + vlen = tiles.headOption.map(_.tileParams.core.vLen).getOrElse(0), priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""), mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)), mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)), diff --git a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala index 4c1186b9..e79b6c4e 100644 --- a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala +++ b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.diplomacy.{LazyModule} import org.chipsalliance.cde.config.{Field, Parameters, Config} import freechips.rocketchip.util.{ResetCatchAndSync} import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters} -import freechips.rocketchip.stage.phases.TargetDirKey +import chipyard.stage.phases.TargetDirKey import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} import chipyard.iobinders.HasIOBinders diff --git a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala index 75ca1764..b9c04eb8 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala @@ -3,8 +3,11 @@ package chipyard.stage -import freechips.rocketchip.stage.ConfigsAnnotation -import firrtl.options.{HasShellOptions, ShellOption} +import chisel3.experimental.BaseModule +import firrtl.annotations.{Annotation, NoTargetAnnotation} +import firrtl.options.{HasShellOptions, ShellOption, Unserializable} + +trait ChipyardOption extends Unserializable { this: Annotation => } /** This hijacks the existing ConfigAnnotation to accept the legacy _-delimited format */ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptions { @@ -23,3 +26,41 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio ) ) } + +/** Paths to config classes */ +case class ConfigsAnnotation(configNames: Seq[String]) extends NoTargetAnnotation with ChipyardOption +private[stage] object ConfigsAnnotation extends HasShellOptions { + override val options = Seq( + new ShellOption[Seq[String]]( + longOption = "configs", + toAnnotationSeq = a => Seq(ConfigsAnnotation(a)), + helpText = "", + shortOption = Some("C") + ) + ) +} + +case class TopModuleAnnotation(clazz: Class[_ <: Any]) extends NoTargetAnnotation with ChipyardOption +private[stage] object TopModuleAnnotation extends HasShellOptions { + override val options = Seq( + new ShellOption[String]( + longOption = "top-module", + toAnnotationSeq = a => Seq(TopModuleAnnotation(Class.forName(a).asInstanceOf[Class[_ <: BaseModule]])), + helpText = "", + shortOption = Some("T") + ) + ) +} + +/** Optional base name for generated files' filenames */ +case class OutputBaseNameAnnotation(outputBaseName: String) extends NoTargetAnnotation with ChipyardOption +private[stage] object OutputBaseNameAnnotation extends HasShellOptions { + override val options = Seq( + new ShellOption[String]( + longOption = "name", + toAnnotationSeq = a => Seq(OutputBaseNameAnnotation(a)), + helpText = "", + shortOption = Some("n") + ) + ) +} diff --git a/generators/chipyard/src/main/scala/stage/ChipyardCli.scala b/generators/chipyard/src/main/scala/stage/ChipyardCli.scala index da9311bf..d6071ff3 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardCli.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardCli.scala @@ -9,6 +9,9 @@ trait ChipyardCli { this: Shell => parser.note("Chipyard Generator Options") Seq( + TopModuleAnnotation, + ConfigsAnnotation, + OutputBaseNameAnnotation, UnderscoreDelimitedConfigsAnnotation ).foreach(_.addOptions(parser)) } diff --git a/generators/chipyard/src/main/scala/stage/ChipyardOptions.scala b/generators/chipyard/src/main/scala/stage/ChipyardOptions.scala new file mode 100644 index 00000000..2ed01ef9 --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/ChipyardOptions.scala @@ -0,0 +1,41 @@ +// See LICENSE + +package chipyard.stage + +class ChipyardOptions private[stage] ( + val topModule: Option[Class[_ <: Any]] = None, + val configNames: Option[Seq[String]] = None, + val outputBaseName: Option[String] = None) { + + private[stage] def copy( + topModule: Option[Class[_ <: Any]] = topModule, + configNames: Option[Seq[String]] = configNames, + outputBaseName: Option[String] = outputBaseName, + ): ChipyardOptions = { + + new ChipyardOptions( + topModule=topModule, + configNames=configNames, + outputBaseName=outputBaseName, + ) + } + + lazy val topPackage: Option[String] = topModule match { + case Some(a) => Some(a.getPackage.getName) + case _ => None + } + + lazy val configClass: Option[String] = configNames match { + case Some(names) => + val classNames = names.map{ n => n.split('.').last } + Some(classNames.mkString("_")) + case _ => None + } + + lazy val longName: Option[String] = outputBaseName match { + case Some(name) => Some(name) + case _ => + if (!topPackage.isEmpty && !configClass.isEmpty) Some(s"${topPackage.get}.${configClass.get}") else None + } +} + diff --git a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala index def8dd90..717a9f95 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala @@ -7,25 +7,35 @@ import chisel3.stage.{ChiselCli, ChiselStage} import firrtl.options.PhaseManager.PhaseDependency import firrtl.options.{Phase, PreservesAll, Shell} import firrtl.stage.FirrtlCli -import freechips.rocketchip.stage.RocketChipCli -import freechips.rocketchip.system.RocketChipStage import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency} import firrtl.options.phases.DeletedWrapper +final class ChipyardChiselStage extends ChiselStage { + + override val targets = Seq( + Dependency[chisel3.stage.phases.Checks], + Dependency[chisel3.stage.phases.Elaborate], + Dependency[chisel3.stage.phases.AddImplicitOutputFile], + Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile], + Dependency[chisel3.stage.phases.MaybeAspectPhase], + Dependency[chisel3.stage.phases.Emitter], + Dependency[chisel3.stage.phases.Convert] + ) + +} + class ChipyardStage extends ChiselStage { - override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli + override val shell = new Shell("chipyard") with ChipyardCli with ChiselCli with FirrtlCli override val targets: Seq[PhaseDependency] = Seq( - Dependency[freechips.rocketchip.stage.phases.Checks], - Dependency[freechips.rocketchip.stage.phases.TransformAnnotations], - Dependency[freechips.rocketchip.stage.phases.PreElaboration], - // Note: Dependency[RocketChiselStage] is not listed here because it is - // package private, however it is named as a prereq for the passes below. - Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - Dependency[freechips.rocketchip.stage.phases.AddDefaultTests], + Dependency[chipyard.stage.phases.Checks], + Dependency[chipyard.stage.phases.TransformAnnotations], + Dependency[chipyard.stage.phases.PreElaboration], + Dependency[ChipyardChiselStage], + Dependency[chipyard.stage.phases.GenerateFirrtlAnnos], Dependency[chipyard.stage.phases.AddDefaultTests], Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags], - Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts], + Dependency[chipyard.stage.phases.GenerateArtefacts], ) override final def invalidates(a: Phase): Boolean = false } diff --git a/generators/chipyard/src/main/scala/stage/StageUtils.scala b/generators/chipyard/src/main/scala/stage/StageUtils.scala new file mode 100644 index 00000000..6cfa7174 --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/StageUtils.scala @@ -0,0 +1,48 @@ +// See LICENSE + +package chipyard.stage + +import java.io.{File, FileWriter} + +import org.chipsalliance.cde.config.{Config, Parameters} +import chisel3.internal.firrtl.Circuit +import freechips.rocketchip.util.{BlackBoxedROM, ROMGenerator} + +trait HasChipyardStageUtils { + + def getConfig(fullConfigClassNames: Seq[String]): Config = { + new Config(fullConfigClassNames.foldRight(Parameters.empty) { case (currentName, config) => + val currentConfig = try { + Class.forName(currentName).newInstance.asInstanceOf[Config] + } catch { + case e: java.lang.ClassNotFoundException => + throw new Exception(s"""Unable to find part "$currentName" from "$fullConfigClassNames", did you misspell it or specify the wrong package path?""", e) + } + currentConfig ++ config + }) + } + + def enumerateROMs(circuit: Circuit): String = { + val res = new StringBuilder + val configs = + circuit.components flatMap { m => + m.id match { + case rom: BlackBoxedROM => Some((rom.name, ROMGenerator.lookup(rom))) + case _ => None + } + } + configs foreach { case (name, c) => + res append s"name ${name} depth ${c.depth} width ${c.width}\n" + } + res.toString + } + + def writeOutputFile(targetDir: String, fname: String, contents: String): File = { + val f = new File(targetDir, fname) + val fw = new FileWriter(f) + fw.write(contents) + fw.close + f + } + +} diff --git a/generators/chipyard/src/main/scala/stage/package.scala b/generators/chipyard/src/main/scala/stage/package.scala new file mode 100644 index 00000000..5dc89f9c --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/package.scala @@ -0,0 +1,24 @@ +// See LICENSE + +package chipyard + +import firrtl.AnnotationSeq +import firrtl.options.OptionsView + +package object stage { + + implicit object ChipyardOptionsView extends OptionsView[ChipyardOptions] { + + def view(annotations: AnnotationSeq): ChipyardOptions = annotations + .collect { case a: ChipyardOption => a } + .foldLeft(new ChipyardOptions()){ (c, x) => + x match { + case TopModuleAnnotation(a) => c.copy(topModule = Some(a)) + case ConfigsAnnotation(a) => c.copy(configNames = Some(a)) + case OutputBaseNameAnnotation(a) => c.copy(outputBaseName = Some(a)) + } + } + + } + +} diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 2258228e..01e963d1 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -10,25 +10,23 @@ import org.chipsalliance.cde.config.Parameters import chisel3.stage.phases.Elaborate import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, NoTargetAnnotation} -import firrtl.options.{Phase, PreservesAll, Dependency} -import firrtl.options.Viewer.view -import freechips.rocketchip.stage.RocketChipOptions -import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} +import firrtl.options._ +import firrtl.options.Viewer._ import freechips.rocketchip.system.{RocketTestSuite, TestGeneration} import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem} -import freechips.rocketchip.util.HasRocketChipStageUtils import freechips.rocketchip.tile.XLen import chipyard.TestSuiteHelper import chipyard.TestSuitesKey +import chipyard.stage._ -class AddDefaultTests extends Phase with HasRocketChipStageUtils { - // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase - // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). - override val prerequisites = Seq( - Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - Dependency[freechips.rocketchip.stage.phases.AddDefaultTests]) - override val dependents = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags]) +/** Annotation that contains a list of [[RocketTestSuite]]s to run */ +case class ChipyardTestSuiteAnnotation(tests: Seq[RocketTestSuite]) extends NoTargetAnnotation with Unserializable + + +class AddDefaultTests extends Phase with PreservesAll[Phase] with HasChipyardStageUtils { + override val prerequisites = Seq(Dependency[ChipyardChiselStage]) + override val dependents = Seq(Dependency[GenerateTestSuiteMakefrags]) private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = { val annotations = mutable.ArrayBuffer[Annotation]() @@ -40,18 +38,16 @@ class AddDefaultTests extends Phase with HasRocketChipStageUtils { // If a custom test suite is set up, use the custom test suite annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p)) - RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations.toSeq + ChipyardTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations.toSeq } override def transform(annotations: AnnotationSeq): AnnotationSeq = { val (testSuiteAnnos, oAnnos) = annotations.partition { - case RocketTestSuiteAnnotation(_) => true + case ChipyardTestSuiteAnnotation(_) => true case o => false } - implicit val p = getConfig(view[RocketChipOptions](annotations).configNames.get).toInstance - addTestSuiteAnnotations ++ oAnnos + implicit val p = getConfig(view[ChipyardOptions](annotations).configNames.get).toInstance + addTestSuiteAnnotations(p) ++ oAnnos } - - override final def invalidates(a: Phase): Boolean = false } diff --git a/generators/chipyard/src/main/scala/stage/phases/Checks.scala b/generators/chipyard/src/main/scala/stage/phases/Checks.scala new file mode 100644 index 00000000..465f673a --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/phases/Checks.scala @@ -0,0 +1,47 @@ +// See LICENSE + +package chipyard.stage.phases + +import firrtl.AnnotationSeq +import firrtl.annotations.Annotation +import firrtl.options.{OptionsException, Phase, PreservesAll, TargetDirAnnotation} +import chipyard.stage._ + +import scala.collection.mutable + +/** Checks for the correct type and number of command line arguments */ +class Checks extends Phase with PreservesAll[Phase] { + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + val targetDir, topModule, configNames, outputBaseName = mutable.ListBuffer[Annotation]() + + annotations.foreach { + case a: TargetDirAnnotation => a +=: targetDir + case a: TopModuleAnnotation => a +=: topModule + case a: ConfigsAnnotation => a +=: configNames + case a: OutputBaseNameAnnotation => a +=: outputBaseName + case _ => + } + + def required(annoList: mutable.ListBuffer[Annotation], option: String): Unit = { + if (annoList.size != 1) { + throw new OptionsException(s"Exactly one $option required") + } + } + + def optional(annoList: mutable.ListBuffer[Annotation], option: String): Unit = { + if (annoList.size > 1) { + throw new OptionsException(s"Too many $option options have been specified") + } + } + + required(targetDir, "target directory") + required(topModule, "top module") + required(configNames, "configs string (','-delimited)") + + optional(outputBaseName, "output base name") + + annotations + } + +} diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateArtefacts.scala b/generators/chipyard/src/main/scala/stage/phases/GenerateArtefacts.scala new file mode 100644 index 00000000..f05d2279 --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/phases/GenerateArtefacts.scala @@ -0,0 +1,26 @@ +// See LICENSE + +package chipyard.stage.phases + +import firrtl.AnnotationSeq +import firrtl.options.{Dependency, Phase, PreservesAll, StageOptions} +import firrtl.options.Viewer.view +import chipyard.stage._ +import freechips.rocketchip.util.{ElaborationArtefacts} + +/** Writes [[ElaborationArtefacts]] into files */ +class GenerateArtefacts extends Phase with PreservesAll[Phase] with HasChipyardStageUtils { + + override val prerequisites = Seq(Dependency[chipyard.stage.ChipyardChiselStage]) + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + val targetDir = view[StageOptions](annotations).targetDir + + ElaborationArtefacts.files.foreach { case (extension, contents) => + writeOutputFile(targetDir, s"${view[ChipyardOptions](annotations).longName.get}.${extension}", contents ()) + } + + annotations + } + +} diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateFirrtlAnnos.scala b/generators/chipyard/src/main/scala/stage/phases/GenerateFirrtlAnnos.scala new file mode 100644 index 00000000..7e19d406 --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/phases/GenerateFirrtlAnnos.scala @@ -0,0 +1,36 @@ +// See LICENSE + +package chipyard.stage.phases + +import firrtl.AnnotationSeq +import firrtl.annotations.{DeletedAnnotation, JsonProtocol} +import firrtl.options.Viewer.view +import firrtl.options._ +import chipyard.stage._ + +/** Writes FIRRTL annotations into a file */ +class GenerateFirrtlAnnos extends Phase with PreservesAll[Phase] with HasChipyardStageUtils { + + override val prerequisites = Seq(Dependency[chipyard.stage.ChipyardChiselStage]) + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + val targetDir = view[StageOptions](annotations).targetDir + val fileName = s"${view[ChipyardOptions](annotations).longName.get}.anno.json" + + val annos = annotations.view.flatMap { + // Remove TargetDirAnnotation so that we can pass as argument to FIRRTL + // Remove CustomFileEmission, those are serialized automatically by Stages + case (_: Unserializable | _: TargetDirAnnotation | _: CustomFileEmission) => + None + case DeletedAnnotation(_, (_: Unserializable | _: CustomFileEmission)) => + None + case a => + Some(a) + } + + writeOutputFile(targetDir, fileName, JsonProtocol.serialize(annos.toSeq)) + + annotations + } + +} diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala index e0796db5..78dd3b96 100644 --- a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala +++ b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala @@ -9,10 +9,8 @@ import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, NoTargetAnnotation} import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable, Dependency} import firrtl.options.Viewer.view -import freechips.rocketchip.stage.RocketChipOptions -import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} +import chipyard.stage._ import freechips.rocketchip.system.TestGeneration -import freechips.rocketchip.util.HasRocketChipStageUtils trait MakefragSnippet { self: Annotation => def toMakefrag: String @@ -21,19 +19,19 @@ trait MakefragSnippet { self: Annotation => case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable /** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */ -class GenerateTestSuiteMakefrags extends Phase with HasRocketChipStageUtils { +class GenerateTestSuiteMakefrags extends Phase with HasChipyardStageUtils { // Our annotations tend not to be serializable, but are not marked as such. - override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + override val prerequisites = Seq(Dependency[chipyard.stage.phases.GenerateFirrtlAnnos], Dependency[chipyard.stage.phases.AddDefaultTests]) override def transform(annotations: AnnotationSeq): AnnotationSeq = { val targetDir = view[StageOptions](annotations).targetDir - val fileName = s"${view[RocketChipOptions](annotations).longName.get}.d" + val fileName = s"${view[ChipyardOptions](annotations).longName.get}.d" val makefragBuilder = new mutable.StringBuilder() val outputAnnotations = annotations.flatMap { - case RocketTestSuiteAnnotation(tests) => + case ChipyardTestSuiteAnnotation(tests) => // Unfortunately the gen method of TestGeneration is rocketchip package // private, so we either have to copy code in or use the stateful form TestGeneration.addSuites(tests) diff --git a/generators/chipyard/src/main/scala/stage/phases/PreElaboration.scala b/generators/chipyard/src/main/scala/stage/phases/PreElaboration.scala new file mode 100644 index 00000000..68992e7c --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/phases/PreElaboration.scala @@ -0,0 +1,43 @@ +// See LICENSE + +package chipyard.stage.phases + +import chisel3.RawModule +import chisel3.stage.ChiselGeneratorAnnotation +import firrtl.AnnotationSeq +import firrtl.options.Viewer.view +import firrtl.options.{Dependency, Phase, PreservesAll, StageOptions} +import org.chipsalliance.cde.config.{Field, Parameters} +import freechips.rocketchip.diplomacy._ +import chipyard.stage._ + +case object TargetDirKey extends Field[String](".") + +/** Constructs a generator function that returns a top module with given config parameters */ +class PreElaboration extends Phase with PreservesAll[Phase] with HasChipyardStageUtils { + + override val prerequisites = Seq(Dependency[Checks]) + override val dependents = Seq(Dependency[chisel3.stage.phases.Elaborate]) + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + + val stageOpts = view[StageOptions](annotations) + val rOpts = view[ChipyardOptions](annotations) + val topMod = rOpts.topModule.get + + val config = getConfig(rOpts.configNames.get).alterPartial { + case TargetDirKey => stageOpts.targetDir + } + + val gen = () => + topMod + .getConstructor(classOf[Parameters]) + .newInstance(config) match { + case a: RawModule => a + case a: LazyModule => LazyModule(a).module + } + + ChiselGeneratorAnnotation(gen) +: annotations + } + +} diff --git a/generators/chipyard/src/main/scala/stage/phases/TransformAnnotations.scala b/generators/chipyard/src/main/scala/stage/phases/TransformAnnotations.scala new file mode 100644 index 00000000..0b66f6a6 --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/phases/TransformAnnotations.scala @@ -0,0 +1,21 @@ +// See LICENSE + +package chipyard.stage.phases + +import chisel3.stage.ChiselOutputFileAnnotation +import firrtl.AnnotationSeq +import firrtl.options.Viewer.view +import firrtl.options.{Dependency, Phase, PreservesAll} +import chipyard.stage._ + +/** Transforms RocketChipAnnotations into those used by other stages */ +class TransformAnnotations extends Phase with PreservesAll[Phase] with HasChipyardStageUtils { + + override val prerequisites = Seq(Dependency[Checks]) + override val dependents = Seq(Dependency[chisel3.stage.phases.AddImplicitOutputFile]) + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + /** Construct output file annotation for emission */ + new ChiselOutputFileAnnotation(view[ChipyardOptions](annotations).longName.get) +: annotations + } +} diff --git a/generators/chipyard/src/main/scala/upf/UPFAspect.scala b/generators/chipyard/src/main/scala/upf/UPFAspect.scala index 65508684..7561e05d 100644 --- a/generators/chipyard/src/main/scala/upf/UPFAspect.scala +++ b/generators/chipyard/src/main/scala/upf/UPFAspect.scala @@ -4,7 +4,7 @@ package chipyard.upf import chisel3.aop.{Aspect} import firrtl.{AnnotationSeq} import chipyard.harness.{TestHarness} -import freechips.rocketchip.stage.phases.{TargetDirKey} +import chipyard.stage.phases.{TargetDirKey} import freechips.rocketchip.diplomacy.{LazyModule} abstract class UPFAspect[T <: TestHarness](upf: UPFFunc.UPFFunction) extends Aspect[T] { diff --git a/generators/constellation b/generators/constellation index 8184e0e7..03ed9e4e 160000 --- a/generators/constellation +++ b/generators/constellation @@ -1 +1 @@ -Subproject commit 8184e0e7e32ff11dce344c449158aa7551e164e0 +Subproject commit 03ed9e4ecd31d71d4bd48f02b0e806bc2b8a7e6b diff --git a/generators/fft-generator b/generators/fft-generator index f598d0c3..811951b4 160000 --- a/generators/fft-generator +++ b/generators/fft-generator @@ -1 +1 @@ -Subproject commit f598d0c359c896e7853c8ef01c39ebecdd48b344 +Subproject commit 811951b44a113f87710a6abaae4582120c1194ba diff --git a/generators/gemmini b/generators/gemmini index f13847e8..8c8b38b9 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit f13847e839baee4a3c8d5d51e76a3dc9e9c1933f +Subproject commit 8c8b38b9dea3e4d6ba9695346a883b2094bd7388 diff --git a/generators/hardfloat b/generators/hardfloat new file mode 160000 index 00000000..d93aa570 --- /dev/null +++ b/generators/hardfloat @@ -0,0 +1 @@ +Subproject commit d93aa570806013dea479a92ba9bb33d1f2d4f69f diff --git a/generators/hwacha b/generators/hwacha index d01ca1e7..bf799dc4 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit d01ca1e7f8a3ba3f419509273dfef00e41095f6a +Subproject commit bf799dc48293cb5017ed2ec22c5023de8d461184 diff --git a/generators/rocket-chip b/generators/rocket-chip index 92b9a01c..2ebc6f1d 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 92b9a01c3d0dd36f4c41bfcb0d9dde25a03f44da +Subproject commit 2ebc6f1d396e23108ab58822089923b938a23019 diff --git a/generators/sha3 b/generators/sha3 index eb3822a2..5e49347f 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit eb3822a2bcc33d5b36456b537681da626ab4b2af +Subproject commit 5e49347f069c72eeb3bf23f1a09170b3cfd3eb2e diff --git a/generators/shuttle b/generators/shuttle index 3c15591a..e628836c 160000 --- a/generators/shuttle +++ b/generators/shuttle @@ -1 +1 @@ -Subproject commit 3c15591a9ee237bb1251e5362de22ad19f64ba07 +Subproject commit e628836c3c4bfe29927cd9e1473801fab33dee6c diff --git a/generators/sifive-blocks b/generators/sifive-blocks index abf129a3..5edd72e7 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit abf129a33bf3d73dbc017f34862038b6e722b8ed +Subproject commit 5edd72e793ccb534b1395d0d8c1831754fd72fec diff --git a/generators/testchipip b/generators/testchipip index 19522315..c80ec1cd 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 1952231569c939a9a5e47fa2eef8168405d0136d +Subproject commit c80ec1cd799cd1d004dad1c381f3e7eac3ebdbcd diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index bd723595..d15498ea 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -102,11 +102,14 @@ cd "$RDIR" toolchains/libgloss \ generators/sha3 \ generators/gemmini \ + generators/rocket-chip \ sims/firesim \ software/nvdla-workload \ software/coremark \ software/firemarshal \ software/spec2017 \ + tools/dsptools \ + tools/rocket-dsp-utils \ vlsi/hammer-mentor-plugins do "$1" "${name%/}" @@ -132,10 +135,19 @@ cd "$RDIR" git submodule update --init generators/gemmini git -C generators/gemmini/ submodule update --init --recursive software/gemmini-rocc-tests + # Non-recursive clone + git submodule update --init generators/rocket-chip + # Minimal non-recursive clone to initialize sbt dependencies git submodule update --init sims/firesim git config --local submodule.sims/firesim.update none + # Non-recursive clone + git submodule update --init tools/rocket-dsp-utils + + # Non-recursive clone + git submodule update --init tools/dsptools + # Only shallow clone needed for basic SW tests git submodule update --init software/firemarshal ) diff --git a/scripts/sbt-launch.jar b/scripts/sbt-launch.jar new file mode 100644 index 00000000..de00d065 Binary files /dev/null and b/scripts/sbt-launch.jar differ diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index 04274910..bfeb7b12 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,30 +1,28 @@ diff --git a/build.sbt b/build.sbt -index ec36a85f..c0c2849a 100644 +index 302d99e6..0aa0fcb4 100644 --- a/build.sbt +++ b/build.sbt -@@ -146,7 +146,7 @@ lazy val testchipip = (project in file("generators/testchipip")) - +@@ -148,7 +148,7 @@ lazy val testchipip = (project in file("generators/testchipip")) + lazy val chipyard = (project in file("generators/chipyard")) .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches -+// sha3, // On separate line to allow for cleaner tutorial-setup patches - dsptools, `rocket-dsp-utils`, ++ //sha3, // On separate line to allow for cleaner tutorial-setup patches + dsptools, rocket_dsp_utils, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, constellation, mempress, barf, shuttle) -@@ -204,11 +204,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) +@@ -220,10 +220,10 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) - + -lazy val sha3 = (project in file("generators/sha3")) - .dependsOn(rocketchip, midasTargetUtils) - .settings(libraryDependencies ++= rocketLibDeps.value) -- .settings(chiselTestSettings) - .settings(commonSettings) -+//lazy val sha3 = (project in file("generators/sha3")) -+// .dependsOn(rocketchip, midasTargetUtils) -+// .settings(libraryDependencies ++= rocketLibDeps.value) -+// .settings(chiselTestSettings) -+// .settings(commonSettings) - ++// lazy val sha3 = (project in file("generators/sha3")) ++// .dependsOn(rocketchip, midasTargetUtils) ++// .settings(libraryDependencies ++= rocketLibDeps.value) ++// .settings(commonSettings) + lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip) diff --git a/sims/firesim b/sims/firesim index 7cade060..67e70ec9 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 7cade06041e372f103c1b22fbb49aeb525aed871 +Subproject commit 67e70ec96d70ebfae5c335dc2ea82dbe91c179e5 diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index e85d2923..5a499ef7 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit e85d2923a5e4fdd7d61cd0cc9f0685c97f451769 +Subproject commit 5a499ef718bba2fc323e9771ebd7545c66825ff6 diff --git a/tools/barstools b/tools/barstools index 400ce780..f5fe37c4 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 400ce780a9b59a4a617e3ae9dbd0e97ca8e802ab +Subproject commit f5fe37c4bf0a37eb5033eeaf930c337895470607 diff --git a/tools/dsptools b/tools/dsptools index 5b1e7335..7bd039fb 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 5b1e733596a39f6960bf9a7c1897d82912372766 +Subproject commit 7bd039fb5f28ce2f31ed4420deb9a2220542838d diff --git a/tools/fixedpoint b/tools/fixedpoint new file mode 160000 index 00000000..35dda166 --- /dev/null +++ b/tools/fixedpoint @@ -0,0 +1 @@ +Subproject commit 35dda166f58f021cc32d00a2e76a5a33691c2b20 diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils index fe641d1c..341e9198 160000 --- a/tools/rocket-dsp-utils +++ b/tools/rocket-dsp-utils @@ -1 +1 @@ -Subproject commit fe641d1c346d5605f95d235e8c75d0baac7fa6d8 +Subproject commit 341e91985fdda7cce7eb30566fe58482a6f5aa40 diff --git a/variables.mk b/variables.mk index 1b6322ad..a3755a3c 100644 --- a/variables.mk +++ b/variables.mk @@ -251,7 +251,7 @@ SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) # passes $(JAVA_TOOL_OPTIONS) from env to java export SBT_OPTS ?= -Dsbt.ivy.home=$(base_dir)/.ivy2 -Dsbt.global.base=$(base_dir)/.sbt -Dsbt.boot.directory=$(base_dir)/.sbt/boot/ -Dsbt.color=always -Dsbt.supershell=false -Dsbt.server.forcestart=true -SBT ?= java -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) +SBT ?= java -jar $(base_dir)/scripts/sbt-launch.jar $(SBT_OPTS) # (1) - classpath of the fat jar # (2) - main class