Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging.

fpga/src/main/scala/arty/TestHarness.scala

@@ -2,13 +2,25 @@ package chipyard.fpga.arty
 
 import chisel3._
 import chisel3.experimental.{Analog}
-
+import scala.collection.mutable.{ArrayBuffer}
 import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.config.{Parameters}
-
+import freechips.rocketchip.config.{Field, Parameters}
 import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
-
 import chipyard.{BuildTop, HasHarnessSignalReferences}
+import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
+
+trait HasTestHarnessFunctions {
+  val lazySystem: LazyModule
+  val harnessFunctions = ArrayBuffer.empty[HasHarnessSignalReferences => Seq[Any]]
+  val portMap = scala.collection.mutable.Map[String, Seq[Data]]()
+}
+
+trait HasHarnessSignalReferences {
+  def harnessClock: Clock
+  def harnessReset: Reset
+  def dutReset: Reset
+  def success: Bool
+}
 
 class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences {
 
@@ -29,6 +41,9 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
   val dutReset = reset_core
 
   // must be after HasHarnessSignalReferences assignments
-  ldut.harnessFunctions.foreach(_(this))
+  ldut match { case d: HasTestHarnessFunctions =>
+    d.harnessFunctions.foreach(_(this))
+    ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap)
+  }
 }