wu-arch/chipyard
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Merge pull request #828 from ucb-bar/async-serial

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Add option to add async queues between chip-serialIO and harness serdes
This commit is contained in:
Abraham Gonzalez
2021-03-19 19:01:25 -07:00
committed by GitHub
parent f52822ff7a c5e7d8a9b2
commit 262c5c8204
3 changed files with 17 additions and 8 deletions
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16
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -242,8 +242,11 @@ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system) implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port => ports.map({ port =>
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
SerialAdapter.tieoff(ram.module.io.tsi_ser) withClockAndReset(th.harnessClock, th.harnessReset) {
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
SerialAdapter.tieoff(ram.module.io.tsi_ser)
}
}) })
} }
}) })
@@ -252,9 +255,12 @@ class WithSimSerial extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system) implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port => ports.map({ port =>
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, port.clock, th.harnessReset.asBool) withClockAndReset(th.harnessClock, th.harnessReset) {
when (success) { th.success := true.B } val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.harnessClock, th.harnessReset.asBool)
when (success) { th.success := true.B }
}
}) })
} }
}) })

7
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -70,8 +70,11 @@ class WithSerialBridge extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => { (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => {
ports.map { port => ports.map { port =>
implicit val p = GetSystemParameters(system) implicit val p = GetSystemParameters(system)
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
SerialBridge(port.clock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) val ram = withClockAndReset(th.harnessClock, th.harnessReset) {
SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
}
SerialBridge(th.harnessClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
} }
Nil Nil
} }

2
generators/testchipip

Submodule generators/testchipip updated: 282ca2e25e...ca3cc6245c