[skip ci] trying ENABLE_CUSTOM_FIRRTL_PASS=1 for Yosys, clarify init script for private tech plugins

docs/VLSI/Advanced-Usage.rst

@@ -3,6 +3,18 @@
 Advanced Usage
 ==============
 
+Hammer Development
+------------------
+If you need to develop Hammer within Chipyard, you will not use the ``hammer-vlsi`` package as installed by conda.
+
+First, clone the `Hammer repository <https://github.com/ucb-bar/hammer>`__ somewhere else on your disk. Then:
+
+.. code-block:: shell
+    
+    pip install -e <path/to/hammer>
+
+Finally, you will need to override the ``site_packages_dir`` variable in ``vlsi/Makefile`` to point to the abspath of your Hammer repository.
+
 Alternative RTL Flows
 ---------------------
 The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom Verilog module through, one only needs to append the following environment variables to the ``make buildfile`` command (or edit them directly in the Makefile).

docs/VLSI/Basic-Flow.rst

@@ -7,22 +7,24 @@ Using Hammer To Place and Route a Custom Block
 
 Initialize the Hammer Plug-ins
 ----------------------------------
-In the Chipyard root, ensure that you have the Chipyard conda environment activated. Then, run:
+In the Chipyard root, ensure that you have the Chipyard conda environment activated. Then, depending on if you are using a technology plugin included with Hammer (ASAP7, Sky130) or as a separate plugin, you will run either of the commands below.
+
+For Hammer-provided plugins (``<tech-plugin-name>`` is ``asap7`` or ``sky130``):
 
 .. code-block:: shell
 
     ./scripts/init-vlsi.sh <tech-plugin-name>
 
-This will pull the Hammer & CAD tool plugin submodules, assuming the technology plugins are available on github.
-Currently only the asap7 and sky130 technology plugins are available on github.
-If you have additional private technology plugins (this is a typical use-case for proprietry process technologies with require NDAs and secure servers), you can submodule them directly
-into VLSI directory with the name ``hammer-<tech-plugin-name>-plugin``.
+For separate technology plugins (this is a typical use-case for proprietry process technologies with require NDAs and secure servers), submodule them directly
+into VLSI directory with the name ``hammer-<tech-plugin-name>-plugin`` before calling the ``init-vlsi.sh`` script.
 For example, for an imaginary process technology called tsmintel3:
 
 .. code-block:: shell
 
     cd vlsi
     git submodule add git@my-secure-server.berkeley.edu:tsmintel3/hammer-tsmintel3-plugin.git
+    cd -
+    ./scripts/init-vlsi.sh tsmintel3
 
 
 .. Note:: Some VLSI EDA tools are supported only on RHEL-based operating systems. We recommend using Chipyard on RHEL7 and above. However, many VLSI server still have old operating systems such as RHEL6, which have software packages older than the basic chipyard requirements. In order to build Chipyard on RHEL6, you will likely need to use tool packages such as devtoolset (for example, devtoolset-8) and/or build from source gcc, git, gmake, make, dtc, cc, bison, libexpat and liby.

docs/VLSI/Sky130-OpenROAD-Tutorial.rst

@@ -87,6 +87,7 @@ which will cause additional variables to be set in ``tutorial.mk``, a few of whi
 * ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
 * ``VLSI_OBJ_DIR=build-sky130-openroad`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity.
 * ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs.
+* ``ENABLE_CUSTOM_FIRRTL_PASS = 1`` is required for synthesis through Yosys. This reverts to the Scala FIRRTL Compiler so that unsupported multidimensional arrays are not generated in the Verilog.
 
 Running the VLSI Flow
 ---------------------