Clean up radiance configs

generators/chipyard/src/main/scala/config/RadianceConfigs.scala

@@ -8,9 +8,6 @@ import freechips.rocketchip.subsystem.WithExtMemSize
 import freechips.rocketchip.tile.XLen
 import org.chipsalliance.cde.config.Config
 import radiance.memory._
-// --------------
-// Rocket Configs
-// --------------
 
 class WithRadROMs(address: BigInt, size: Int, filename: String) extends Config((site, here, up) => {
   case RadianceROMsLocated() => Some(up(RadianceROMsLocated()).getOrElse(Seq()) ++
@@ -31,86 +28,12 @@ class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigIn
     ))
 })
 
-class RocketDummyVortexConfig extends Config(
+// ----------------
-  new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
+// Radiance Configs
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
+// ----------------
-  new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
-  new WithExtMemSize(BigInt("80000000", 16)) ++
-  new testchipip.soc.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++
 
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
+class RadianceBaseConfig extends Config(
-
+  new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 4) ++
-  new AbstractConfig)
-
-class RocketGPUConfig extends Config(
-  new radiance.subsystem.WithNCustomSmallRocketCores(2) ++          // multiple rocket-core
-  new chipyard.config.AbstractConfig)
-
-class RadianceROMConfig extends Config(
-  new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
-  new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  // new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
-  new WithExtMemSize(BigInt("80000000", 16)) ++
-  new WithRadBootROM() ++
-  new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
-  new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++
-  new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
-  new AbstractConfig)
-
-class RadianceROMNoCoalConfig extends Config(
-  new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
-  // new radiance.subsystem.WithCoalescer(nNewSrcIds = 16, enable = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
-  new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  // new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
-  new WithExtMemSize(BigInt("80000000", 16)) ++
-  new WithRadBootROM() ++
-  new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
-  new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++
-  new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
-  new AbstractConfig)
-
-class RadianceROMLargeConfig extends Config(
-  new radiance.subsystem.WithRadianceCores(4, useVxCache = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
-  new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  // new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
-  new WithExtMemSize(BigInt("80000000", 16)) ++
-  new WithRadBootROM() ++
-  new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
-  new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++
-  new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
-  new AbstractConfig)
-
-class RadianceROMCacheConfig extends Config(
-  new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
-  new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
-  new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
-  new WithExtMemSize(BigInt("80000000", 16)) ++
-  new WithRadBootROM() ++
-  new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
-  new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++
-  new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
-  new AbstractConfig)
-
-class RadianceROMCacheNoCoalConfig extends Config(
-  new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
-  // new radiance.subsystem.WithCoalescer(nNewSrcIds = 16, enable = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
-  new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
-  new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
   new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
   new WithExtMemSize(BigInt("80000000", 16)) ++
@@ -121,6 +44,33 @@ class RadianceROMCacheNoCoalConfig extends Config(
   new AbstractConfig)
 
 class RadianceConfig extends Config(
+  new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
+  new radiance.subsystem.WithCoalescer(nNewSrcIds = 4) ++
+  new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++
+  new RadianceBaseConfig)
+
+class RadianceNoCacheConfig extends Config(
+  new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
+  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
+  new RadianceBaseConfig)
+
+class RadianceNoCoalConfig extends Config(
+  new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
+  new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++
+  new RadianceBaseConfig)
+
+class RadianceNoCacheNoCoalConfig extends Config(
+  new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new RadianceBaseConfig)
+
+class RadianceLargeConfig extends Config(
+  new radiance.subsystem.WithRadianceCores(4, useVxCache = false) ++
+  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
+  new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++
+  new RadianceBaseConfig)
+
+class RadianceNoROMConfig extends Config(
   new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
   new WithExtMemSize(BigInt("80000000", 16)) ++
@@ -128,12 +78,19 @@ class RadianceConfig extends Config(
   new testchipip.soc.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++
   new AbstractConfig)
 
-class RadianceConfigVortexCache extends Config(
+class RadianceFuzzerConfig extends Config(
+  new radiance.subsystem.WithFuzzerCores(1, useVxCache = false) ++
+  new radiance.subsystem.WithCoalescer(nNewSrcIds = 4, enable = true) ++
+  new radiance.subsystem.WithSimtLanes(nLanes = 16, nSrcIds = 4) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++
+  new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
+  new WithExtMemSize(BigInt("80000000", 16)) ++
+  new AbstractConfig)
+
+class RadianceOldCacheConfig extends Config(
   new radiance.subsystem.WithRadianceCores(1, useVxCache = true) ++
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  // new freechips.rocketchip.subsystem.WithNoMemPort ++
-  // new testchipip.WithSbusScratchpad(banks=2) ++
-  // new testchipip.soc.WithMbusScratchpad(banks=2) ++
   new WithExtMemSize(BigInt("80000000", 16)) ++
   new WithRadBootROM() ++
   new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
@@ -141,3 +98,22 @@ class RadianceConfigVortexCache extends Config(
   new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
   new AbstractConfig
 )
+
+// --------------------
+// Rocket-based Configs
+// --------------------
+
+class RocketDummyVortexConfig extends Config(
+  new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
+  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
+  new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
+  new WithExtMemSize(BigInt("80000000", 16)) ++
+  new testchipip.soc.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new AbstractConfig)
+
+class RocketGPUConfig extends Config(
+  new radiance.subsystem.WithNCustomSmallRocketCores(2) ++
+  new chipyard.config.AbstractConfig)