From 28664ea8df7ea9f53f5d31e7cf313559821601a8 Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Thu, 26 Sep 2019 09:50:41 -0700 Subject: [PATCH] Update section header on Verilog support in chipyard tools --- docs/Customization/Incorporating-Verilog-Blocks.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Customization/Incorporating-Verilog-Blocks.rst b/docs/Customization/Incorporating-Verilog-Blocks.rst index 2052eec6..8aecde15 100644 --- a/docs/Customization/Incorporating-Verilog-Blocks.rst +++ b/docs/Customization/Incorporating-Verilog-Blocks.rst @@ -158,8 +158,8 @@ write. :start-after: DOC include start: GCD test :end-before: DOC include end: GCD test -Support for Verilog in Downstream Berkeley Tools ------------------------------------------------- +Support for Verilog Within Chipyard Tool Flows +---------------------------------------------- There are important differences in how Verilog blackboxes are treated by downstream tools. Since they remain blackboxes in FIRRTL, their