From 73dc1dfe6fdcb0412ae5000ae02c5db12c1ab1c8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 25 Jun 2019 07:59:35 -0700 Subject: [PATCH 1/4] bump rocket and testchipip --- generators/rocket-chip | 2 +- generators/testchipip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index b8baef6f..50de8a34 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit b8baef6f26fa36c9b4e0b2a5eec12cd76ae5daf8 +Subproject commit 50de8a34c19c12de5066cd7ada50ebb5f5b2ea26 diff --git a/generators/testchipip b/generators/testchipip index cd176871..855a4dd4 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit cd1768712ead82d1a76278b65b7f6ea41ae82dc9 +Subproject commit 855a4dd4822cee1693fe1e0bf7d0727f074ceae5 From ef1620b753ca1d24d71c0187116e995f39ad406c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 6 Jul 2019 15:13:37 -0700 Subject: [PATCH 2/4] update verilator.mk to support different install location --- sims/verisim/verilator.mk | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/sims/verisim/verilator.mk b/sims/verisim/verilator.mk index 4edfa6e3..80abd869 100644 --- a/sims/verisim/verilator.mk +++ b/sims/verisim/verilator.mk @@ -5,9 +5,10 @@ ######################################################################################### # verilator version, binary, and path ######################################################################################### -VERILATOR_VERSION=4.016 -VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION) -INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator) +VERILATOR_VERSION = 4.016 +VERILATOR_INSTALL_DIR ?= verilator +VERILATOR_SRCDIR = $(VERILATOR_INSTALL_DIR)/src/verilator-$(VERILATOR_VERSION) +INSTALLED_VERILATOR = $(abspath $(VERILATOR_INSTALL_DIR)/install/bin/verilator) ######################################################################################### # build and install our own verilator to work around versioning issues @@ -25,15 +26,15 @@ $(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile $(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure mkdir -p $(dir $@) - cd $(dir $@) && ./configure --prefix=$(abspath verilator/install) + cd $(dir $@) && ./configure --prefix=$(abspath $(VERILATOR_INSTALL_DIR)/install) -$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz +$(VERILATOR_SRCDIR)/configure: $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz rm -rf $(dir $@) mkdir -p $(dir $@) cat $^ | tar -xz --strip-components=1 -C $(dir $@) touch $@ -verilator/verilator-$(VERILATOR_VERSION).tar.gz: +$(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz: mkdir -p $(dir $@) wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ From 87e4090e3861251d02322fca63648153f5ed2619 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 8 Jul 2019 14:31:41 -0700 Subject: [PATCH 3/4] bump boom | correct error on first cmd in pipe --- common.mk | 4 ++-- generators/boom | 2 +- sims/verisim/Makefile | 2 +- sims/vsim/Makefile | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/common.mk b/common.mk index 310da07c..1b0d139d 100644 --- a/common.mk +++ b/common.mk @@ -76,7 +76,7 @@ verilog: $(sim_vsrcs) # helper rules to run simulator ######################################################################################### run-binary: $(sim) - $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) ######################################################################################### # run assembly/benchmarks rules @@ -89,7 +89,7 @@ $(output_dir)/%.run: $(output_dir)/% $(sim) $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< && touch $@ $(output_dir)/%.out: $(output_dir)/% $(sim) - $(sim) $(PERMISSIVE_ON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@) ######################################################################################### # include build/project specific makefrags made from the generator diff --git a/generators/boom b/generators/boom index 80a68074..84879571 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 80a680745c27dfe54bdd217e8de9c24c1c96b553 +Subproject commit 848795715f721b6a88887283179176474a1496b8 diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 655d67cc..629373c8 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -84,7 +84,7 @@ $(sim_debug): $(model_mk_debug) # helper rules to run simulator with debug ######################################################################################### run-binary-debug: $(sim_debug) - $(sim_debug) $(SIM_FLAGS) -v$(sim_out_name).vcd $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out + (set -o pipefail && $(sim_debug) $(SIM_FLAGS) -v$(sim_out_name).vcd $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) ######################################################################################### # create a verisim vpd rule diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index d34fb5eb..f5882757 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -90,7 +90,7 @@ $(sim_debug) : $(sim_vsrcs) $(sim_dotf) # helper rules to run simulator with debug ######################################################################################### run-binary-debug: $(sim_debug) - $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) +vcdplusfile=$(sim_out_name).vpd $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) +vcdplusfile=$(sim_out_name).vpd $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) ######################################################################################### # create a vcs vpd rule From a408422ac18d7062cc0a2f3bb265eff6e63eab6d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 8 Jul 2019 14:34:17 -0700 Subject: [PATCH 4/4] reverse @zhemao commit on htif: need to parse args for verilator --- .../utilities/src/main/resources/csrc/emulator.cc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index b4f2e093..1a4f4dd2 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -121,6 +121,7 @@ int main(int argc, char** argv) FILE * vcdfile = NULL; uint64_t start = 0; #endif + char ** htif_argv = NULL; int verilog_plusargs_legal = 1; while (1) { @@ -242,6 +243,10 @@ done_processing: usage(argv[0]); return 1; } + int htif_argc = 1 + argc - optind; + htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); + htif_argv[0] = argv[0]; + for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++]; if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); @@ -264,8 +269,8 @@ done_processing: #endif jtag = new remote_bitbang_t(rbb_port); - dtm = new dtm_t(argc, argv); - tsi = new tsi_t(argc, argv); + dtm = new dtm_t(htif_argc, htif_argv); + tsi = new tsi_t(htif_argc, htif_argv); signal(SIGTERM, handle_sigterm); @@ -346,5 +351,6 @@ done_processing: if (tsi) delete tsi; if (jtag) delete jtag; if (tile) delete tile; + if (htif_argv) free(htif_argv); return ret; }