From 2b4fb555af8dc06c8f6fe19c32d1002afebc0f09 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 12:15:19 -0800 Subject: [PATCH] Use ProjectRef for FIRRTL and use it for firrtl-interpreter --- build.sbt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index e58e7d60..51172677 100644 --- a/build.sbt +++ b/build.sbt @@ -81,9 +81,12 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin -lazy val chisel = (project in file("tools/chisel3")) +lazy val chisel = (project in file("tools/chisel3")) + +lazy val firrtl = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) + .dependsOn(firrtl) .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) @@ -107,7 +110,8 @@ lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") // Rocket-chip dependencies (subsumes making RC a RootProject) lazy val hardfloat = (project in rocketChipDir / "hardfloat") - .settings(commonSettings).dependsOn(midasTargetUtils) + .dependsOn(midasTargetUtils) + .settings(commonSettings) lazy val rocketMacros = (project in rocketChipDir / "macros") .settings(commonSettings)